| Home | Terms of Use | Site Map | Contact Us |
IndustryCommunity.com > Electrical and Electronic Community > Printed Circuit Designers' Forum > Message
Main Menu
Glossary of Printed Circuit Design and Manufacturing
Find

[ List Subjects ][ Current Board ][ Post Message ]
[ View Followups ][ Post Followup ]

Subject: Re: p.c.b forum

Date: 05/03/00 at 2:12 PM
Posted by: John W. Childers
E-mail: jwchilders@goldengategraphics.com
Message Posted:

In Reply to: p.c.b forum posted by Shoshi on 05/03/00 at 8:28 AM:

These are good questions.

Note: any terms below unique to PCB design can be found in my “Glossary for Printed Circuit Design and Manufacturing.?(http://personal.idcomm.com/childers/PCGLOSS.htm). Please let me know if I left any terms out, or if you would like some terms added to it.

Before designing your board, consult with the manufacturers who are most likely to build it: your own qualified vendors. Find out what they would want.

In America, the most common material for PCB's is a copper epoxy laminate called FR4. There are many other materials such as Teflon and ceramic, which are esoteric, expensive and have special uses that take advantage of their unique properties.

The most common American finish is Solder Coat over Solder Mask over Bare Copper (SMOBC). The older finish, “Reflow?or tin-lead plate, has dropped some in use due to the toxic lead content, but is still widely used on prototype boards. Another finish good for its flatness (eliminating solder bumps with fine pitch SMT) is Electroless Gold Over Electroless Nickel (also called “Flash Gold?. Also good for its flatness is Organic Non-Oxidizing Coatings, which are on the rise in place of solder coat and flash gold, especially for BGA's.

Trace sizes and spacing can go down to 4 mils (0.1 mm) at some board houses, but much more common for SMT is 8 mil traces and 7 mil spaces (which adds up to 15, keeping things on a handy 5 mil grid).

But the bigger the traces, the better. I often use 12 mil traces and 12 mil spacing if I have room.

The pad sizes are controlled by the size of the foot of the SMT lead, adding room for solder fillets. The most common pad width I have used for fine pitch (down to .65mm, although I have seen .5mm) parts like TQFP's is 11 mils. This is basically the max width of the lead itself. The room for the solder fillet is added at the ends, and I use a length of 79 mils for these pads, allowing for variations in manufacture.

More common is 50-mil-pitch SMT SOIC's and PLCC's. For these I use a 24x90 mil pad. The extra length allows for solder fillet and variation in packages.

I use 24 mil width, not 25. I like to use multiples of eight for SMT pad widths and to use only drawn, not flashed rectangles. “Pieces of Eight?is my cute name for the use of multiples of 8 in pad sizes (in metric this equates nicely to multiples of 0.2mm). This allows me to have a master aperture list of manageable size. It includes all multiples of eight, both round and square, up to 400 mils, my maximum aperture width. Thus any pad aperture will have its corresponding solder mask clearance (8 mils larger). For 50 mil pitch parts and discrete SMT’s, I build all my parts this way.

(Example: the 1206 capacitor is specified by IPC as 63 mil square pad, 63 mils being the nominal width of the part itself. I use 64 mils, which is well within the manufacturing tolerances (+ or ?3 mils) of the part itself.).

It turns out the multiples of 8 all land within manufacturing tolerances of all of the IPC standard footprints for discretes. If in doubt, I go a little larger, always allowing plenty of room for the solder fillets.

The smallest through via (but not the absolute smallest) is drilled with a 16-mil bit. After plating, this nominally results in a 12-mil hole. Anything smaller and the manufacturing cost goes way up. I use as large a via as the design will tolerate (up to the smallest through hole for components.) If I can get away with a 32 mil via hole, I'll use that, because that allows boards to be drilled in a stack instead of one at a time, saving manufacturing costs. If the via is carrying a lot of current, I enlarge it to accommodate that. I figure the circumference of the hole ought to be at least as large as the trace width, if not larger, since the plating in the hole usually won't be as thick as the copper clad on the board.

I hope this helps, and welcome any comments from other designers.


Follow Ups:


Post a Follow-up:

Name:
E-Mail:
Subject:

Message to Post:

 

1999-2001 Sunlit Technology Co., Ltd. All rights reserved.