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Subject: Re: Pspice simulation
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Date: 10/23/03 at 5:04 PM
Posted by: Russ Kincaid
E-mail: russlk-nospam[AT55]yahoo.com (replace [AT55] with @ to reply)
In Reply to: Pspice simulation posted by Dominique Ferron on 10/23/03 at 3:35 PM:
It is not necessary to do that. The .TRAN statement has the form: .TRAN[/OP][]
The symbols  indicate an optional input.
/OP causes the output to contain a table of node voltages calculated as initial bias points.
PRINT INTERVAL is the time step used in the printout.
FINAL TIME is the time the simulation ends.
NO-PRINT INTERVAL is the time delay before printout starts. This is the parameter you need to set at 1mS or more.
STEP CEILING is the maximum time step used in the simulation. If you do not specify, the time step will be 1/50 of the final time. This will be too large in your case so you need to set it at something less than 1/4 cycle.
If you don't have "SPICE a guide to Circuit Simulation & Analysis Using PSpice" by Paul W. Tuinenga, you should get it.
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