In Reply to: Re: How to recover clock from Manchester Encoded Data? posted by Russ Kincaid on 07/04/03 at 1:14 PM:
Thanks for some of your inputs. I am also facing similar problem to decode manchester data. My requirement is on chip decoding. I have followed the following methodolgy and faced few problems. If any idea let me know what are the solutions.
1. I know the frequency of the manchester data. ie. 1 Mbps. So I have a clock of 16 MHz as input my chip. I have used the 16 Mhz clock and done double sampling with the both the edges of the clock, since I don't have a PLL to multiply clock. Out of 16 samples of each edge, eight samples for one logic level and 8 samples for another logic level. (as manchester data of 1mbps is 500 ns sec. high and 500 ns low for represent to 1 and vice versa for 0.). This set us is working fine with following pbms.
pbms: Since I don't have any control over the incoming data, when it enters the chip with reference to clock edges, I am facing setup violations either with positive clock decoder or negetive clock decoder, which are inturn getting propogated inside and causing many signals unknown status.
Many of my colegues says, this will not happen in real time chip, because unknown value means it coule be 1 or 0, so there won't be any pbm in real chip. But I am not convinced with that.
So I would like to know, is it correct to use the input clock to decode or is it required to recover the clock using PLL. I would like to know, if PLL is must, is there any way to model synthesizable digitall PLL using verilog or vhdl.
Sorry for a big mail.
any ideas pls help me.