In Reply to: Phase shift a sine-wave to resolve a timing issue. posted by labtech on 10/28/02 at 9:16 AM:
The easiest method I can think of requires you to generate the clock from a phase locked loop (PLL) such as LM565, CD4046, 74HC4046, or 74HC7046. I've posted a block diagram at http://pageproducer.iglide.net/ron.harrison/PLL.html
You need to set the VCO to run at 66kHz. The value of N in the frequency dividers depends on the range of the phase comparator (PC) in the PLL you choose. For instance, if your PC has a range of +/- 90 degrees (as in the LM565, or an exclusive OR), you should set N=4, so that you have +/- 360 degrees of signal at the PC inputs. This may seem like overkill, but setting N=2 will only give you +/- 180 degrees range, which is marginal. N=3 would be good, but you would need to make the waveforms symmetrical (50% duty cycle), which requires a more complicated divider. If your PC has a range of +/- 180 degrees, you can set N=2. If you use the 4046 or 7046, I think you can use PC2, which has a range of +/- 360 degrees, in which case you wouldn't need dividers. You would have to pay special attention to the loop filter, because that PC normally has no ripple component, but if you offset the phase, it will.
If you have more questions, post them here, and I'll try to answer them if I have time.