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Subject: Re: SEQUENCIAL LOGIC

Date: 02/14/02 at 10:47 PM
Posted by: Russ Kincaid
E-mail: russlk@yahoo.com
Message Posted:

In Reply to: SEQUENCIAL LOGIC posted by Adam Webster on 02/12/02 at 4:31 PM:

You must have a clock to tell when the data is valid. A PLD would be the most compact solution, but you can build it with descrete logic. Call the data lines a, b, c where a is the LSB and c is the MSB, /a is inverted a, /b is inverted b, etc. Use 3-input AND gates (or NAND gates are more available) (4023), feed the AND gate output to a set-reset FF. {Ok, scratch the clock, I am thinking as I am writing}. The FF goes to an 8-input AND gate ( or use an inverted NOR). You can use the CW output to reset the CCW channel & vice-versa. You won't know which way it is going until one revolution is completed.


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