In Reply to: SEQUENCIAL LOGIC posted by Adam Webster on 02/12/02 at 4:31 PM:
Unfortunately, the description you give is not complete enough to produce equations or a state diagram. When you say '2 outputs' do you mean to have 2 physically separate outputs, one to decode each of the sequences you give? Or one physical output that will become true when either of the above sequences is detected?
Also, is there a clock signal that validates the 3 inputs - or are the sequences to be decoded asynchronously?
How are the output(s) to respond? Presumably, you'd like an output to go from false to true once a complete sequence is detected, and stay true so long as the sequence continues correctly, but go false as soon as an incorrect input is received. But is the correct sequence to be detected only when it starts with the first input vector you give, or is it to be detected when starting at any of the inputs?
Lastly, in what technology do you hope to implement the solution? Discrete logic, a microcontroller, or a programmable logic device (PLD) are all possibilities, and will affect the way in which the solution is expressed. For someone having a logic compiler for a PLD, the solution can be produced quite quickly (that is, for a synchronous design), but I am not really set up to do this at present.
Whatever the answers to all these questions are, the underlying design technique to be used is called a 'finite state machine', and almost any logic design textbook should describe this.