| Home | Terms of Use | Site Map | Contact Us |
IndustryCommunity.com > Electrical and Electronic Community > Analog Circuit Design Forum > Message
Main Menu
Find

[ List Subjects ][ Main Page ]
[ View Followups ][ Post Followup ]

Subject: Re: Clock extraction circuit

Date: 05/31/02 at 4:45 PM
Posted by: Ron Harrison
E-mail: rmaxh@yahoo.com
Message Posted:

In Reply to: Re: Clock extraction circuit posted by Dave Bell on 05/31/02 at 11:52 AM:

Dave, you can recover a 2F (32kHz) signal by running the modulated carrier through a squarer. You can divide that by two to get 16kHz, with ambiguous phase (0/180) relative to the data.

A simple PLL will not give you a stable carrier if you have random data. Imagine string of 1's that is so long that the PLL tracks the carrier phase. Then a long string of 0's comes along, inverting the phase. The loop will unlock, then relock. Now imagine a long string of 10101010..., where the phase flips on every bit. The loop will never lock, because it never has time to.

Regarding suppressed carrier - the modulated data stream IS suppressed carrier, with double sidebands. The location and shape of the sidebands depends on the data.

I'm trying to imagine why you want to extract the carrier, but have no interest in recovering data. Care to share that reason?

Ron H


Follow Ups:


Post a Follow-up:

Name:
E-Mail:
Subject:

Message to Post:

 

1999-2001 Sunlit Technology Co., Ltd. All rights reserved.