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Subject: Re: Adding a DC bias to a differential clock signal

Date: 04/09/02 at 7:53 AM
Posted by: David Ashby
E-mail: dashby@quin.co.uk
Message Posted:

In Reply to: Adding a DC bias to a differential clock signal posted by Mario Santos on 04/08/02 at 1:08 PM:

Hi Mario,

Another idea is to use a capacitor in the signal line, and then add resistors on the receiver side of the capacitor to provide the correct bias voltage for the receiver input. If you use two resistors as a potential divider between the 5V and 0V supply rails, you can work out the ratio of resistor values you need to get +1.65V; at the same time, the resistors will appear in parallel to the incoming signal, thus providing a termination impedance. Therefore, choose values which (in parallel) will give you the desired termination impedance.

This scheme assumes that you are always transmitting a clock, and it is not required to transmit a high or low D.C. level.

David Ashby.


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