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Subject: Re: Time Devaition and Phase jitter in PLL
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Date: 10/11/01 at 7:19 AM
Posted by: David Ashby
In Reply to: Time Devaition and Phase jitter in PLL posted by Arun Sharma on 10/08/01 at 4:39 AM:
Just a suggestion:
Are you able to observe the PFD output? You could try looking at it while the PLL is in lock, and then see what happens when you introduce a small phase shift or frequency change to the input signal.
Another approach is to do some open-loop testing of the PFD to check the linearity of its phase-to-output-voltage transfer function, but that might not be possible if your PLL is in silicon.
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