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Subject: Re: Need peak detector circuit schematics.

Date: 10/10/01 at 8:40 AM
Posted by: David Ashby
E-mail: dashby@quin.co.uk
Message Posted:

In Reply to: Need peak detector circuit schematics. posted by Anders Dahlberg on 09/28/01 at 11:32 AM:

Hello Anders,

The circuit you describe is almost there! All you need do to overcome the non-linearity of the diode is to take the feedback to the (-) input of the op-amp from the other side of the diode.

The circuit for detecting positive peaks is then as follows:

Input to op-amp (+) input;
Op-amp output to diode anode;
Diode cathode to capacitor, and op-amp (-) input
- this is the positive peak output.

The negative peak circuit will be the same except the diode is reversed.

One or two caveats: The circuit will only work accurately over a limited bandwidth, mainly because of slew-rate, and output limitations of the op-amp. Choice of op-amp will affect this. Also, you may need to check that the op-amp remains stable while charging the capacitor during an input peak.

To reduce errors due to loading on the capacitor, use a second op-amp as a voltage follower connected to the capacitor.

To reset the peak detector, you could use a FET or analogue switch (e.g. CMOS 4066) across the capacitor.

There are some other tricks to extend the peak hold time (reduce leakage currents) if necessary.

Hope this helps,

David Ashby

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