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Date: 10/08/01 at 4:39 AM
Posted by: Arun Sharma
E-mail: arun1077@yahoo.com

Hi,

I am evaluating PLL in silicon. I saw large time daviation in
the output clock, which PLL corrects after a a long time. I suspect that it may due to
metastabilty or dead zone in the PFD. I couldn't understand how i can test whether its due to PFD or not.
Comments and suggestion to confirm this in simulations are most welcome.
Please suggest how one can correlate time deviation with phase jitter.

Best Regards
Arun

Follow Ups:

  Re: Time Devaition and Phase jitter in PLL David Ashby   Posted at: 10/11/01 (0)

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