| Home | Terms of Use | Site Map | Contact Us |
IndustryCommunity.com > Electrical and Electronic Community > Analog Circuit Design Forum > Message
Main Menu
Find

[ List Subjects ][ Main Page ]
[ View Followups ][ Post Followup ]

Subject: Isochronous Clock Extraction

Date: 03/06/01 at 5:12 PM
Posted by: Simon Denvir
E-mail: simon.denvir@clara.co.uk
Message Posted:

I`m trying to develop a USB transciever from "building block" logic, I can implement nearly all of the functions except the clock recovery module. USB specs state that a packet will start with a 12MHz sync sequence 01010100. I
guess a PLL would track this pulse train and generate a phase accurate and frequency accurate facsimile over the period of the ensuing packet, the trouble is I`m not sure how to implement this on a PLL, since the input signal would be removed after the inital sync sequence. Any ideas?

Simon Denvir


Follow Ups:


Post a Follow-up:

Name:
E-Mail:
Subject:

Message to Post:

 

1999-2001 Sunlit Technology Co., Ltd. All rights reserved.