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Date: 03/06/01 at 5:12 PM
Posted by: Simon Denvir
E-mail: simon.denvir@clara.co.uk

I`m trying to develop a USB transciever from "building block" logic, I can implement nearly all of the functions except the clock recovery module. USB specs state that a packet will start with a 12MHz sync sequence 01010100. I
guess a PLL would track this pulse train and generate a phase accurate and frequency accurate facsimile over the period of the ensuing packet, the trouble is I`m not sure how to implement this on a PLL, since the input signal would be removed after the inital sync sequence. Any ideas?

Simon Denvir

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