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Subject: Re: Egroup for Analog Design (Spice/Pspice Club) : Electronic Career Center !

Date: 06/11/01 at 3:40 PM
Posted by: Derek Johns
E-mail: derek.johns@timedomain.com
Message Posted:

In Reply to: Egroup for Analog Design (Spice/Pspice Club) : Electronic Career Center ! posted by Spice boy on 05/14/01 at 3:28 AM:

I'm not sure if this is an appropriate place to post a career opportunity with our exciting pre-IPO company. If not, please forgive me. If so, and you are interested in the following position or know qualified candidates, please call or e-mail me at your earliest convenience.

I really appreciate your help with this critical recruiting effort.


Derek Johns
Time Domain Corporation
7057 Old Madison Pike
Huntsville, AL 35806
(256) 428-6475 (o)
(256) 759-0334 (cell)

Position Title: Silicon Germanium Physical Design Engineer
Purpose of the Position (why does the company need this position to succeed?):
Engineer needed for physical design / layout of RF, analog and mixed-signal integrated circuits in SiGe BiCMOS.

Job Responsibilities (what is this person going to be responsible/accountable for?):

Responsible for full-custom physical design from schematics, including optimization for performance/area, LVS, DRC, tape-outs and documentation. He/she will be responsible for the circuit design, performance, verification and organization of all physical design activity.

Must have good knowledge of IC layout techniques. Candidate should be familiar with appropriate Cadence CAD tools. Good understanding of different layers and also some understanding of their electrical nature. Should be familiar with design rule analysis, parasitic extraction, noise and crosstalk issues, power management techniques, yield improvement and manufacturability issues, and design for test techniques.

Requirements (yrs/type of experience, education):

Silicon Germanium high performance circuit design experience a plus. Place and Route methodologies a plus. Knowledge of submicron design issues a plus. DRC, LVS, extraction experience a plus. Exposure to many different circuit techniques a plus. Knowledge of static timing model formats a plus. Experience in transistor level circuits and a solid understanding of device physics a plus.

Should have good interpersonal skills. Detail oriented, independent, and able to make good decisions. Requires as MSEE degree or equivalent and 3+ years of applicable experience. Must have experience in physical layout design.

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