In Reply to: Synchronous counter circuit diagram posted by Ramasawmy on 07/04/01 at 6:44 AM:
I, Mr Ramasawmy is asking you if you can send me the answer to the question below, please:
Using JK flip flops and NAND gates, design a synchronous counter, which in addition to its clock input has a control input R. If R=1, the counter is to operate as a divide by 3 network. If R=0, the counter is to hold its present value and not change its output when a clock pulse occurs. Draw the state diagram as part of your design.
Thank you in advance, Ramasawmy.