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Subject: Need a synchronous counter circuit diagram.
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Date: 07/04/01 at 6:27 AM
Posted by: Ramasawmy
In Reply to: need ecg-circuit diagram posted by Dirk Schramm on 02/02/01 at 3:31 AM:
Please can you send me the answer to the question below:
Using JK flip flops and NAND gates, design a synchronous counter, which in addition to its clock input has a control input R. If R=1, the counter is to operate as a divide by 3 network. If R=0, the counter is to hold its present value and not change its output when a clock pulse occurs. Draw the state diagram as part of your design.
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