In Reply to: Re: AD9854 DDS chip posted by M Clavet on 08/09/00 at 2:48 PM:
We finally figured out what the problem was. The timing diagrams in the Rev 0 AD9854 data sheet
are not quite right. After hooking up a logic analyzer to the Analog AD9854 demo board, we found that
the timing of the data lines should match that shown for the address lines (instead of being offset as
they show it). In hindsight, this makes sense.
Also, if you change to external IOUD mode, you need to wait until one more internal IOUD occurs
for it to take effect.
After changing the timing, things work great.