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Subject: Re: Opening for VLSI Backend Designers

Date: 04/19/03 at 6:57 AM
Posted by: ARIMILLI RAJESH
E-mail: arimilli_r@yahoo.co.in
Message Posted:

In Reply to: Re: Opening for VLSI Backend Designers posted by chevva kishore on 10/31/02 at 3:54 AM:

RESUME

Arimilli Rajesh,
Plot No: 109,
1st Block
Sathya Kalayani(R.B.R) Complex,
Miyapur,
Hyderabad-50.
Ph: 9849479589
E-Mail: arimilli_r@yahoo.co.in


CARRIER OBJECTIVE:

Seeking an entry level in an Organization that provides a professional work atmosphere and ample opportunities to put my interpersonal skills in practice and flexibility to adapt to new technologies in the ever-changing field of software industries.

EDUCATIONAL QUALIFICATIONS:

Bachelor of Engineering in electronics communications from Gudlavalleru engineering college in gudlavalleru in may 2002.
WORK EXPERIENCE:
Worked as an backend engineer in ttm India Pvt Ltd in hyderabad.
EDA Tools:
Cadence tools


Layout Editor : Virtuoso
Physical Verification : Diva
Floor-Planner & Place : First Encounter
Place & Route : Silicon Ensemble

Timing Analyzer : Pearl
CrossTalk/NoiseAnalysis : CeltIC


COMPUTER KNOWLEDGE:

Operating systems : Unix,Linux,MS-Dos, WINDOWS-98/95/2000/me.
Programming Languages : C, C + +, VHDL, ASSEMBLY LANGUAGE.
Web Technologies : HTML, JAVA SCRIPT.

Project #1:

Standard Cell Library Development


Tools Used : Layout editor Virtuoso

Description : Designed about 10 Standardcells
(JKFFSRXL, SDFFSRX2, EDFFTRX1, DFFRHQX4, TLATSNX4 TLATRXL etc.)

Technology : 0.18micron (tsmc0.18)


Project #2


Design 8085 Microprocessor


Tools Used : Virtuoso,Diva,First Encounter,Silicon Ensemble,Pearl,Celtic

Description : Generating an 8x256 Memory Module using Cadence
Memory compiler, Place and Route different blocks like
Memory, CPU using Cadence, Timing closure using Pearl and
Physical Verification using Diva (DRC, LVS).

Project # 3

Design Pico Java Processor

Tools Used : Virtuoso,Diva,First Encounter,Silicon Ensemble,Pearl,Celtic

Description : Hierarchical floor planning using First Encounter, Route Different
Blocks using Silicon Ensemble , timing closure using Pearl, parasitic
extraction using Celtic and Physical verification using
Diva(DRC, LVS).

4#Design a Timing Critical Block

Tools Used : Virtuoso,Diva,First Encounter,Silicon Ensemble,Pearl,Celtic

Description : Import and Preparing Data using , Timing Driven
Placement using First Encounter , Skew requirements achieved using
Pearl, , some violations in critical paths were fixed manually
and finally run Diva for fixing DRC and LVS errors. Verification using
Diva.
Project # 5

Design of Java Processor

Tools Used : Cadence tools First Encounter, Silicon Ensemble, Pearl,
Virtuoso,Diva
Description : Hierarchical floor planning using First Encounter, Route different blocks using Silicon Ensemble, Timing analysis using Pearl, Physical verification using Diva
Project # 6

Design of PCI block

Tools Used : Cadence tools- First Encounter,Silicon Ensemble, Pearl,
Virtuoso, DIva.

Description : Floor planning using First Encounter, Route Different blocks
using Silicon Ensemble, Timing analysis using Pearl, Physical verification using Diva.

PROJECT WORK:

The aim of our project is to develop an UNDER WATER LOGIC SEQUENCER in vhdl using cpld (complex programmable logic device). The advent of fast, high-density cpld’s has opened up an exiting new area of applications of developing logic blocks upon requirement. Many simple logic functions can run much faster in dedicated hardware than through the traditional PCB layout.
We have wri we have written code for chip select generation, sensing discrete inputs, generating discrete outputs and wait state generation and simulated the design code in the ACTIVE HDL system environment and successfully completed our project. This chip is going to be used in the control of lca (light combat aircraft). Our logic sequencer, which automatically controls the faulted subsystem using VHDL.

ACADEMIC QUALIFICATIONS:

1.BACHELOR IN ELECTRONICS&COMMUNICATIONS ENGINEERING
Name of Instute: GUDLAVALLERU ENGG COLLEGE
Duration: 1998-2002
University:JAWAHAR LAL NEHRU TECHNOLOGICAL UNIVERSITY
Percentage:67%
2.INTERMEDIATE
Duration:1996-1998
Percentage:82.7%
3.S.S.C
Percentage:82%

PERSONAL PROFILE:

Name :ARIMILLI RAJESH

Father’s Name : A.SURYA RAO

Date of Birth :10-04-1981.

Martial Status : Single.

Languages known : Telugu, Hindi & English.

Strengths : Hard Working and Sensual Response.



(ARIMILLI RAJESH)


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