T.D. MANOJ KUMAR REDDY
192,1st floor,adarsh complex, N.R.layout,
Garvebhavi playa,Hosur Road,Bangalore-68
Ph: 51119537 e-mail : firstname.lastname@example.org, email@example.com
CAREER OBJECTIVE :
To achieve efficiency and a challenging position in Digital design ,VLSI and Embedded systems,development with the state of art technology where my analytical skills and creativity can be put in for successful completion of project.
EDUCATIONAL QUALIFICATIONS : -
B.E.(ECE) from SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY
Affiliated to BANGALORE University in MAR-2001.
Working as Hard ware Engineer in S.V.TECHNOLOGIES, from june2001 Hyderabad.
Research & Development of required logic and testing, Implementing the desired logic programming it on EPLD’S(EPM3032ALC44-4) Using ALTERA- MAX-PLUS II Software and test on the PCB.
TECHNICAL SKILLS :-
Operating Systems : MS-DOS ,Windows 95/98
Low level Programming Languages : 8085,8086
High level Programming Languages : c,c++
Hardware Descriptive Languages : VHDL
Hardware Descriptive Tools : Altera-Max-Plus-II, Leonardo Spectrum
Date of Birth : 18 APR 1978
Father : T.D.Mohan Reddy.
Nationality : Indian
Sex : Male
Languages Known : English, Hindi, Telugu, and Kannada.
ü “Clock Recovery And Synchronization Of Digital Data Communication System”
Team size : Four
Duration : 4 months
Organization : L.R.D.E,DRDO, Bangalore
The project is used to recover the clock from the transmitted data and synchronization of received digital data.
Clock Recovery: -
The receiver requires proper clock information to decode the received data without error. The clock recovery circuit is used to recover the clock information from the received data stream.
It is required to recognize the start and end of each frame to separate the various fields from frame. The synchronization circuitry uses the sync bit format to achieve synchronization. A suitable algorithm should be devised to achieve synchronization even in the presence of imitation.
Field combination : -
The frame consists of three parts they are, 8-bit synchronization slot,8-bit control signal slot & 16-bit data slot. All these bits are generated by different sections but before frame transmission all these bits have to be grouped together to form a single frame.
ü HIGH BIT RATE “BIT ERROR RATE” SYSTEM (BER)
(For 90 Mhz &110Mhz Clock. Using Discrete circuits ALTERA EPLD’S))
Team size : Two
Client : ISRO,Bangalore
v TRANSMETER END :
§ Data Generator : It generates psaudo random data of 10^15 –1 and 10^23 –1 code lengths from input clock.
§ Encoder : It encodes the data in phase and quarter phase of desired algorithm to the receiver end.
v RECEIVER END
§ Decoder: It decodes the data in phase and quarter phase of desired algorithm from the transmitter end.
§ Error Detector: It to read the errors in data received for 10^15 –1 and 10^23 –1 code lengths.
§ Prescaler circuit: It prescale the clock for displaying the clock on the frequency counter.
§ Ratio counter and switching: It is used for display the errors and exponent on LED display.
§ Keypad &LCD Display: Selections are selected from the keypad and displayed on LCD display.
I certify that the information I have provided is correct and I shall be wholly responsible if any information is provided to be fake.
Date: (T.D. Manoj Kumar Reddy.)