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Subject: Masters (EE) grad IN BAY AREA looking for Full time/Part time Intern - Anywhere in USA

Date: 09/26/02 at 6:04 PM
Posted by: Chintan Purohit
E-mail: mailchintan@yahoo.com
Message Posted:

Looking for opportunity in ASIC/ VLSI/ Memory Design/ Test/ Product Engineering opportunity.

Profile :
--MSEE with thorough focus on VLSI/ ASIC Design area and one year experience as Hardware Trainee Engineer.

--Working experience with VHDL/ Verilog (ASIC Design flow. RTL Generation for Robot control circuitry, Compiling and simulating using Modelsim, Synthesizing RTL modules using Leonardo,chip level place/route, and chip level design rule verification and LVS, Mapping the design onto XC 4000 Xilinx FPGA), Strong fundamentals in Verilog HDL Coding (Blocking/ Non-Blocking Statements), timing-driven optimization and technology mapping.

--Knowledge of DSM considerations (Body effect, Miller effect, Antenna effect), High-speed signal integrity considerations, RC extraction (Lumped/ Distributive Interconnect Modelling, Parallel plate/ Fringing Capacitance), Crosstalk, Electro migration, Transmission line effects.

--Working knowledge of CMOS IC Design logic and circuit design principles (Inverter characteristics and considerations (Resistive, Pseudo nmos, Static/ Dynamic, tradeoff between area, speed and power) and Mentor EDA tools for physical layout, simulation and synthesis in UNIX environment.

--Participation in projects from concept development to chip fabrication (Logic Optimization, FULL CUSTOM CIRCUIT DESIGN - Electrical model using transistors, MANUAL Layout Design and Optimization for comprising blocks, Generation of CIF file)

--Experience with transistor level (PSPICE) circuit design (I/O Pad Driver Project) and considerations at the design level (Latch up, ESD,Ground Bounce)

--Determination to pursue problems not in books, employing strong fundamentals gained from academic endeavors.

--Team player, good communication skills and the drive to make significant contributions to the company.

Attention: Hiring Personnel

Dear Sir/ Madam,
Good Day to you!!

I am writing to express my interest in ASIC/ VLSI/ Memory Design/ Test/ Product Engineering opportunity.

I am confident to take on hands on responsibility due to my sharp analytical/ judgemental skills coupled with required knowledge.
I have had PROJECT working experience with VHDL/ Verilog (ASIC Design flow. RTL Generation for UART/ Robot control circuitry, Compiling and simulating using Modelsim, Synthesizing RTL modules using Leonardo, chip level place/route and chip level design rule verification and LVS, Mapping the design onto XC 4000 Xilinx FPGA) with complete coursework on VLSI /ASIC Design in my Masters.

I will appreciate if you could skim through my credentials and forward them to concerned hiring personnel.

Attached is my resume along with a small profile enlisting undertaken work for your kind consideration.
Thank you for your time and consideration.
Best Regards,

Chintan Purohit

Chintan Purohit
707 Continental Circle Apt# 624 Mountain View, CA 94040
AVAILIBILITY: September 2002
Cell Phone: (419)-787-8080 Home Phone: 650-965-0721

Objective : Seeking a full time position that will allow me to apply my skills to ASIC Design/ Test/ Product challenges in next-generation computing and communication systems.

CMOS VLSI Design, ASIC Design, High Performance Microprocessor Design, VLSI Testing & Validation, HDL Coding and Synthesis.

Proficient in VLSI Design and ASIC design philosophies.
Solid Knowledge of Logic/ Circuit Design Considerations, Routing and Placement (Signal Integrity) Issues, Digital Design, Programmable ASICs (Programming technologies, logic cells of Xilinx, Actel, I/O and interconnect issues), Cache concepts, pipelining, Hazards, fault models, Constrained Synthesis, Static Timing Analysis, Boundary Scan.
Good interpersonal and documentation skills.
Demonstrated potential to interact productively with admirable organizational capabilities and the drive and determination to get things done.


EDA Tools : Layout Editor, Layout Simulator (Lsim), Leonardo Spectrum, PSPICE, Modelsim, OrCAD, Mentor Graphics Design Architect (Schematic Capture), QuickHDL, Xilinx Foundation Series Design Manager
HDL/ Scripting Languages: VHDL, C, Verilog, HTML, Assembly INTEL 8085,8086
Application Software :MS-OFFICE 97/2000, Frame maker 5.5
Operating Systems : SUN OS 5.7 (Solaris 2.5), UNIX, Windows NT 4.0, Windows 98, DOS

Design and layout of 8 KB SRAM (Control circuit, row & column decoders, memory cells, sense amplifiers) in 0.4 micron technology. Mentor Graphics Led was used to develop the layout and the simulations were carried out using Lsim.

Design and implementation of 8-bit positive integer parallel multiplier.
My role in the project was to come up with the architecture and floor planning along with participation in all the stages of project until chip fabrication. Multiplier cell was implemented using transmission gates. Layout design and simulation were done using Mentor Graphics EDA tools Led and Lsim.

Design of 3.3V I/O Pad Driver circuit to drive a offchip load of 50 pF, input fed from minimum size inverter capacitance of 5fF. Circuit was designed by appropriate sizing of transistors and was simulated using 0.4-micron-process parameters in Pspice.

Design of Phase Locked Loop with operating range 120 to 280 MHz.

Design of Robot control circuitry and mapped the finite state machine VHDL design onto Xilinx XC4003e FPGA. The compiled VHDL code was synthesized using Leonardo.
Design and verification of a full duplex Digital UART.
The design used two independent HDL modules in Verilog,the transmitter and the receiver. The design was compiled, simulated and tested on Modelsim.

MS in Electrical Engineering Focus: VLSI Design
Aug'00-May'02 GPA: 3.75/4.0
The University of Toledo, Ohio

BS in Electrical and Electronics Engineering
June96-July00 GPA: 3.87/4.0
VJTI, University of Mumbai (Bombay), India

Digital VLSI Design I: Basic subsystem design
Field Programmable Gate Arrays
Digital VLSI Design II: Memories and Structured logic design
Digital Design Using VHDL
Digital CMOS / BiCMOS Circuit design
Physical design of VLSI circuits

Graduate Assistant -Engineering Technology Department.
July 2001- Aug 2002
Complete research and design of the Field Programmable Logic Devices [CSET4650] and Assembly Language Programming [EET 2230] Distance Learning courses.

Hardware Trainee Engineer - Lexicon Computers Ltd.
June 1999-July 2000
Experience in trouble shooting computer hardware, maintenance/ installation, upgrading OS and peripherals (FDD/HDD, drives and cards), attending to clients' onsite problems, providing telephonic technical support, administration of networking environments.

Related Undergraduate Courses:
Microcomputer System Design: Pentium Processor Architecture, PCI/SCSI Bus System Architecture. Architecture and Assembly language programming of 8086 and 8085 processors. Networks and Circuit theory.


- Paper "Minimization of test configurations for logic cells of XC 4000 Xilinx FPGAs".
- Secured an Overall Distinction in BS (Honors) Degree from Bombay (Mumbai) University. Ranked in the TOP 2% in the university.
- Recipient of National Talent Search Scholarship for 3 years in India.
- FINALIST in IEEE Bombay section hardware contest titled "Component design: Using MSD-First logic" at Fr.Conceicao Rodrigues College,Bandra Mumbai.
- Stood 15th in the Mumbai Merit list from among more than one hundred- thousand candidates at the Higher Secondary Certificate State Examination (Aggregate Percentage-92.17%)
- "Digit Pipelined Arithmetic For ICs", Second Prize, IEEE Section.

PROFESSIONAL MEMBERSHIPS: Member of The Institution of Electric Engineers (IEE) UK

REFERENCES: Available upon request

AVAILIBILITY: Immediate (Sept. 2002)


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