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Subject: Re: Opening for VLSI Backend Designers

Date: 08/08/02 at 11:13 PM
Posted by: Venkanna Malothu
E-mail: venki_naik146@yahoo.co.in
Message Posted:

In Reply to: Opening for VLSI Backend Designers posted by Kalpa on 04/08/02 at 8:44 AM:

RESUME

Venkanna Malothu
c/o Mr. Ramanna (Owner)
#Door.no .704, 3rd cross,
1st Main, Domlur,
Bangalore-79.
Phone no. 080-5350120

E-mail : venkat_416@rediffmail.com

OBJECTIVE : Seeking a challenging responsibility in the field of Physical Design, layout, Physical Verification (DRC/LVS/ERC/ANT) and RC-Extraction.

SUMMARY OF WORK EXPERIENCE:

* 1 1/2 years of experience:

WORK EXPERIENCE :

October, '01 - July '02, ATIIT Chennai, India

Responsibilities:

- Responsible Digital design, Physical design, layout, DRC/LVS
- Physical verification, DRC, LVS and Antenna using Calibre, Mentor tool
- Involved in Std cells verification, modifying and fixing layout for DRC/LVS clean
using Calibre tools.
- Involved in RC-Extraction, using xCalibre, Mentor tool
- GDSII data generation
- Simulation and design of digital circuits
- Synthesis


Nov. '00 - April '01, ETDC, Hyderabad, India

Responsibilities:

- Design and development of Solid - State Cable Fault Detector
- Implementing hand held battery operated portable unit for detecting the signals.
- Involved in Signal generating and transmitting units implementation.
- Involved in signal generation and amplification unit implementation to operate on 230V AC mains


EDUCATION :

P.G Diploma in Physical Design from ATIIT, Chennai, 2002
BS in Electronics and Communication Engineering, Osmania University, June, 2001


USED FOLLOWING CAD TOOLS :

Calibre: For Design Rule Checking, Layout Vs Schematic reporting
IC-Station : Layout editing, Floorplan, Place & route
Xcalibre: For Parasitic Extraction
Modelsim: For Hardware Simulation
Leonardo: For synthesis
Languages: Hardware implementation languages VHDL & Verilog


Reference: Available up on request


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