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Subject: Re: UL vs IEC Creepage requirements

Date: 02/28/02 at 9:07 PM
Posted by: John Dunn - Consultant
E-mail: ambertec@ieee.org
Message Posted:

In Reply to: Re: UL vs IEC Creepage requirements posted by Tracy Lentz on 02/28/02 at 8:19 PM:

Hi, Tracy.

The answer to your question is: YES! Believe me, this can be serious mischief afoot!

It strikes me that 20 kV is an awful lot of high voltage to have across the foils of a printed circuit board. Corona at the foil edges could be a very, very serious problem to deal with.

I worked at Bertan High Voltage for eleven years and I never once tried that or heard of anybody trying it.

Still, the minimum spacing required for 20 kV, assuming that you are encapsulating your high voltage circuitry, is best taken as being set by a stress of no greater than 10 volts per mil (10000 volts per inch). Hence, 20 kV would take two inches or greater separation.

This 10V per mil factor is used by high voltage connector manufacturers. It is of course, imperative that all surfaces be absolutely clean before encapsulation and it is also helful to roughen insulating surfaces with non-conductive sandpaper (Not emery!!! Emery grains are conductive!!) to increase the net surface area and hence, the creepage distance.

Good luck.

John Dunn - President
Ambertec, Inc.
ambertec@ieee.org


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