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Subject: Re: VLSI and ASIC Designers

Date: 09/17/01 at 9:02 AM
Posted by: DEBI PRASAD DAS
E-mail: debi_das_debi@yahoo.com
Message Posted:

In Reply to: Re: VLSI and ASIC Designers posted by kishore kunal sinha on 07/26/01 at 2:11 PM:

DEBI PRASAD DAS
Dept. of AE & IE,
Regional Engineering College
Rourkela - 769 008
Orissa, INDIA
Ph. - (0661) 571776 (R)
(0661) 570850 (O)
Email - debi_das_debi@yaahoo.com
debi_das@rec1.ren.nic.in

OBJECTIVE: To obtain a position as a Hardware Design Engineer, VLSI and DSP developer

EDUCATION: M.Sc. in Electronics
M. Sc. in Electronics
P.G. Dept.
Sambalpur University, Orissa
1999 First 73.14

Ph.D. in Electronics
R.E.C., RourkelaSambalpur University, Orissa
ACTIVE NOISE CONTROL
Continuing

 COURSES STUDIES IN M.Sc. (ELECTRONICS) :
Semiconductor Devices, Semiconductor Electronics, Digital Electronics, Microprocessor & Applications, Network Theory, Mathematical Methods for Electronics, Computer Programming & Data Structure, Computer Organisation & Architecture, Electromagnetics Antenna & Propagation, Microwave Electronics, Analog & Digital Communication, Signal & Systems, Quantum & Optoelectronics, Instrumentation & Process Control.

 LABORATORY EXPOSURE (M.Sc.) :
Device & Analog Circuit Lab., Computer Programming Lab., Digital Electronics Lab., Microprocessor Lab., Microwave Lab., Design & Simulation Lab. Analog & Digital Communication Lab., Signal Processing Lab..

 PROJECT DEVELOPED :
(M.Sc. level) :Moving Message Display (Hardware)
(Extra) : Automation in Home using 8085 microprocessor

 TRAINING PROGRAM ATTENDED (VLSI and Related Software):
1. Training on SOLARIS and Windows NT Operating System, sponsored by MIT, Govt. of INDIA, at IIT, Kharagpur
2. Xilinx and ModelSim Software training by CG-CorEL, INDIA, Sponsoer by MIT, Govt. of INDIA, at IIT, Kharagpur
3. VHDL, Chip Synthesis & Test synthesis on Synopsys Software training by D'GPRO VLSI Training Center, Sponsored by MIT, Govt. of INDIA, at IIT, Delhi
4. Cadence Design and Flow training by Cadence India, Sponsored by MIT, Govt. of INDIA, at IIT, Kanpur
5. VLSI Subsystem Design IEP training by IC Design Group, CEERI, PILANI, India, sponsored by MIT, Govt. of INDIA.
6. SIMULATION AND MODELING IEP training sponsored by MIT, Govt. of INDIA, at CEDT, IISc, Bangalore.

 Ph.D. TOPIC : Active Noise Control Using DSP and Soft computing Techniques

PERSONAL ACHIEVEMENT :

 SCHOLARSHIP & AWARDS :
National Scholarship in Class X (1991-96) Index no. -210/91

 RESEARCH PUBLICATION :
1. D. P.Das "FPGA IMPLEMENTATION OF ALGORITHM-AGILE ENCRIPTION IN ATM NETWORK" CSI National Conference, Rourkela Chapter.
2. G. Panda, S. K. Meher, D. P. Das "A NOVEL CHARACTER RECOGNITION SCHEME USING RBF NEURAL NETWORK" National Conference on Soft-Computing and Information Technology, Bilaspur, 2000.
3. G. Panda, D. P. Das " ISSUES AND IMPLEMENTATION OF ACTIVE ACOUSTIC NOISE CANCELLER", Accepted for presentation at National Conference CSI, Calcutta Chapter 2001
4. G. Panda and D. P. Das "FIELD PROGRAMABLE GATE ARRAY BASED DESIGN OF ALGORITHM-AGILE ENCRIPTION IN ATM NETWORK" Accepted for presentation at National Conference CSI, Calcutta Chapter 2001
5. G. Panda, D. P. Das " STUDY OF FEED BACK CONSTRAINTS IN ANC AND THE EFFECT OF ON-LINE FEED BACK CANCELLATION", Communicated for Publication to journal of IETE, INDIA.
6. G. Panda, D. P. Das " A NOVEL CONTINUOUS ONLINE FEED BACK CANCELLATION TECHNIQUE FOR SINGLE CHANNEL ACTIVE NOISE CONTROL" Communicated for Publication to 21st IASTED International Conference MIC 2002


7. G. Panda, D. P.Das " HIGHER ORDER STATISTICS BASED TECHNIQUE FOR ESTIMATING THE DEGREE OF NONCAUSALITY IN ACTIVE NOISE CONTROL", Communicated for Publication to journal of IETE, INDIA.
8. G. Panda, Vishal R. Joshi, D.P.Das "A NOVEL SIGMOIDAL NEURAL NETWORK MODEL FOR SYSTEM IDENTIFICATION AND CHANNEL EQUALIZATION" Communicated for Publication to IEE ELECTRONICS LETTERS.


 RESEARCH PROJECTS DEVELOPED :
1. "FPGA IMPLEMENTATION OF DIFFERENT ADDER ARCHITECTURE" (The work is on design and implementation of different adder architectures on XC4000E family Xilinx FPGA by using Xilinx software and VHDL code.
2. "LAYOUT DESIGN, SIMULATION AND VERIFICATION OF DIGITAL IC AND PLA.(Using TANNER TOOLS)"
3. "USING SYNOPSYS SOFTWARE FOR TESTING AND TESTABILITY OF DIGITAL CIRCUITS" (On Going)
4. "ADAPTIVE FILTERING TECHNIQUES FOR CHANNEL EQUALIZATION" (Matlab Simulation and design of LMS, RLS, Neural, Neuro Fuzzy Equalizers for different linear and nonlinear communication channels)
5. "NEURAL NETWORK FOR PATTERN RECOGNITION" (Matlab software is used for simulation. The different types of Neural networks like FLANN, MLANN and RBF based pattern recognition techniques are developed)
6. "A HIGH SPEED ACTIVE NOISE CONTROLLER DESIGN" (On going, Matlab simulation for Fast Adaptive techniques and used in ANC problem to make it faster)
7. "REAL TIME IMPLEMENTATION OF ACTIVE NOISE CONTROLLER" ( On going, Using C program and Dynalog's PCL-208 Data Acquisition card)

 CONFERENCE ATTENDED AND PAPER PRESENTED :
1. NATTIONAL CONFEREENCE ON E-SECURITY & WEB, COMPUTER SOCIETY OF INDIA, ROURKELA CHAPTER Feb. 2nd & 3rd 2001
Paper Presented : FPGA IMPLEMENTATION OF ALGORITHM-AGILE ENCRIPTION IN ATM NETWORK
2. NATIONAL CONFERENCE ON SOFT-COMPUTING AND INFORMATION TECHNOLOGY, BILASPUR, 2000.
Paper Presented : A NOVEL CHARACTER RECOGNITION SCHEME USING RBF NEURAL NETWORK.
WORK EXPERIENCE :

 PRESENT POSITION : Research Asst. in VLSI Design Project Sponsored by Ministry of Information Technology, Govt. of INDIA, in the AE & IE Dept. of REC, Rourkela 769008

 TEACHING EXPERIENCE :
Visiting Faculty at
1. C.V. Raman College of Engg. and Technology, Bhubaneswar for CE-II course of 6th Sem Computer Sc and Engg. The course includes Intel's 8085, 8086 P Zilog's Z-80 P and a no. of interfacing ICs.
2. Purushottam Institute of Engg. And Technology, Rourkela the subject Basic Electronics.
3. C.V. Raman College of Engg. and Technology, Bhubaneswar. For Digital Communication
4. R. E. C. Rourkela, Dept. of AE & IE, Honorary Lecturer for VLSI Design & Techniques.

RESEARCH INTEREST:
Active Noise Control, Development of fast optimization algorithms using DSP Neural Network, Fuzzy Logic, Genetic Algorithms and different statistical methods. Data Acquisition with TMS 320 DSP processors Kit, VLSI Design Electronic Circuit Designing using different analog and digital ICs including microprocessor & implementing them, PC based Automation
REFERENCES:
Prof. (Dr.) G. Panda
Dept. of AE & IE
Regional Engineering College
Rourkela - 769008
Orissa (INDIA)
Email gpanda@rec.ren.nic.in
ganapat@dte.vsnl.net.in

Prof. (Dr.) S.P.Pati
Dept. of Physics.
Sambalpur University,
Jyotivihar, Burla - 768019
Orissa (INDIA)

DECLARATION :
I declare that all the above statements given are true and complete in all respect to the best of my knowledge.


Place :Rourkela
Date :16 September, 2001 DEBI PRASAD DAS


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