In Reply to: Re: VLSI and ASIC Designers posted by S.Balamurugan on 09/03/00 at 2:03 AM:
By surfing the net i have come to know that there is some post vaccant in your company for the ASIC/FPGA chip designing.I found myself eligible for the same.So i am sending my resume towards you for your consideration.Also right now i am learning VHDL.I am waiting for your reply.
Name : SHAH ALPESH POONAMCHAND
Permanent Address : 11,Umangpark Society,
Radhaswami satsang road,
Phone Number : (079)7522860
E-mail : firstname.lastname@example.org
Date of Birth : 9th oct 1976
Nationality : Indian
Educational Qualification : B.E. in Electronics & Communication with first class from S.S.Engg.college Bhavnagar.
Current Activity : Just now I have completed specialized training on ASIC designing.I am Learning following skills:
. Verilog HDL
. PERL script language
. EDA tools
. Simulators and Synthesizers
. Xilinx foundation series
. Active HDL 4.0(ALDEC)
Projects during B.E: Project on Component Location Indicatior At Tata Telecom Gandhinagar.
Working Experience : Worked as a Temporary Engineer in G.C.E.L. Gandhinagar for the
period 3 months.
Also worked as a faculty of C & C++.
* Just now I have completed the project of Programmable 8279 keyboard/display interface in Verilog.
Software knowledge : Having knowledge of programming languages C & C++.
About myself : I always try to be a good student in life learning new skills whenever possible.A strong knowledge thirst drives me to learn whatever new in this technology driven world.