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Subject: Re: VLSI and ASIC Designers

Date: 03/16/01 at 12:16 AM
Posted by: Ashok Alagappan
E-mail: asky01@usa.net
Message Posted:

In Reply to: VLSI and ASIC Designers posted by F-o-r-t-u-n-e Personnel Consultants on 07/14/00 at 10:06 AM:

400, S Oak St, # 118,
March 16,2001

I am Ashok Alagappan and I am a Graduate Student majoring in Electrical Engineering in the University of Texas at Arlington. I learned of your company through the online Career Search database through Career Services at the University and in the website. I conducted some additional research on your organization that leads me to believe there would be a good fit between my skills and interests and your needs. As my Spring Semester has started , I am seeking an opportunity to apply and enhance my knowledge in Electrical Engineering through a summer internship or co-op program in your esteemed Company.
My work background and coursework's have supplied me with many skills and an understanding of the nuances of Electrical Engineering, especially Integrated circuit Design.My present cumulative GPA is 3.67/4.00.

My course work VLSI Design and Technology has provided me with an insight in to Mentor Graphics Tools and its Applications. I have also knowledge in VHDL,RF circuit Design, Analog CMOS IC Design, Semiconductor Device Theory and Digital Signal Processing(DSP). I have extensive Skills in Software Packages and Languages like C, C++ , Assembly Language, Spice and VHDL Coding.

I worked as a Trainee Engineer in E.I.D Parry(INDIA) Ltd. I was assigned the job of operating the electronic control mechanisms for the plant and developing software and testing it for the efficient operation of the plant.
I have been active at Annamlai University as the Chairman of Electrical Engineering Association(EEA), which requires me to organize Technical and Non-technical events for over 400 students.

I have enclosed a copy of my resume with additional information about my qualifications and background. Thank you for your consideration. I look forward to receiving your reply.

Ashok Alagappan.

Ashok Alagappan
400, South Oak St, Apt # 118
Arlington, Texas-76010

OBJECTIVE Seeking a co-op or internship position that will challenge my creativity and determination in the field of Electrical Engineering.

EDUCATION M.S. in Electrical Engineering.
[Aug '00-Present] University of Texas at Arlington,Texas,USA.
Cumulative GPA-3.67/4.00

B.S. in Electrical and Electronics Engineering.
[Aug '96-May'00] Annamalai University, Tamil Nadu, India.
Cumulative GPA-3.9/4.00

VLSI Design and Technology.
Analog CMOS IC Design.
Semiconductor Device Theory.
RF Circuit Design.
Personal computer systems.
Digital signal processing.
Digital Electronics.
Linear and Digital Integrated Circuits Lab
Programming in C and its Applications.

Operating systems Windows 98,windows NT, MS Dos, Unix, Sun Solaris.
Programming Languages C, C++, FORTRAN, Visual Basic, Assembly Language.
Hardware Description/
Simulation Languages VHDL, Spice.
Software Packages MS office, Mentor Graphics, Matlab.


[May '98] E.I.D Parry (India) ltd., India.
Trainee Engineer.
Took training in the control room of the co-generation plant. Training
Included operation and testing of various electronic control mechanisms for the Plant. Gained a great deal of Practical training and Industrial exposure.

[July '99-May '00] Annamalai University, Tamil Nadu, India.
Chairman-(EEA) Electrical Engineering Association, Students Chapter,
Annamalai University.
Job responsibilities included organizing many events like Tech quizzes, debates,
National level seminars, guest lectures and sports competitions.

* "Adaptive fuzzy based speed control of dc motors for Electric Vehicles". Done in collaboration with Central Electro Chemical Research Institute, Karaikudi, Tamil Nadu, India.
Work included the practical load test on DC motors in the Laboratory and simulating the result by developing a fuzzy based software in C++.

* Designed an 8-bit carry look ahead adder circuit for maximum speed and efficiency using Mentor Graphics. The schematics for the adder circuit were done using Design Architect. The schematics were simulated using Quick Sim. Handcrafted Layout was done using IC Station. The optimization for design trade off was satisfactorily checked using Hspice simulations.

* A Diode model was developed based on the physical descriptions of the diode like diffusion geometries, doping and lifetime profiles etc. The values for spice parameters were also been derived. The diffusion technique used was Ion implantation.

* Presented a Technical paper in the Surge-2k, a national level Technical

* Presented a seminar on "C Graphics".

INTEREST Challenging position in Integrated circuit design, manufacturing and Testing.

REFERENCES Available upon Request.

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