In Reply to: VLSI and ASIC Designers posted by F-o-r-t-u-n-e Personnel Consultants on 07/14/00 at 10:06 AM:
I am working as Design Engineer in VLSI. I have One year nad 6 Months
Experience in FPGA. Pl.arrange interview as early as possible.
NAME : S.Balamurugan
E-Mail id : email@example.com
Bachelor's Degree in
Electronics & Communication.
One year and 6 Months in VLSI.
Address for Communication :
Plot No :177, New Vasavi Nagar,
Secunderabad - 500 015.
Rendezvous On Chip (I) Pvt.Ltd
Working as Design Engineer
From March'99 to till date.
Web Site : www.trinc.com
Horizon Semiconductors & Networking Solutions Pvt.ltd
Worked as Design Engineer From Feb'98 to Feb'99.
Title : NETWORK ACCELERATOR CONTROLLER
1.Developing the testbenches Environment
for Validating the NAC features.
2.Running Random Simulation - Sending
different types of Packets from
Implementation : Verilog HDL
Identifying , coding and running the testcases
for all NAC features like NAT,reassembly,
Fragmentation,Adding,Deleting and Querying
the Internet Assosiation.
Description : For Validating the NAC features ,
we developped the host side environment
for setup the descriptors and sending the
different types of packets with all possible
combinations . Here the host is PLX (PCI 9080).
Forming of all the packets in linked list fashion
in host memory for comparing the packets .
We developped the target (ethernet in
both 10/100 mbps) side environment to
send different types of packets with
different errors through MAC model
(LSI 84302) . Forming of all the packets
in ether node memory for comparing all
the packets. We developped the comparision
tasks for comparing of all the packets from
both host and target sides. Identified the
test cases for all types of NAC features.
Contribution : Tested all the NAC features by sending
the different types of packets with
different options. Developped and modified
the test environement to test all the features.
Title : PCI TARGET MODELLING
Responsibility : Designed the Modules by RTL Code
Implementation : VHDL
Description : Configuration Register modeling for
a PCI device.The device is a general
interface which utilises some memory
address phase or I/O address phase.
Functions mainly concerned in
Read And Write Transfer
PCI data transfer.
SPECIAL CYCLE ENABLE
To broadcast a message to one or more target.
Concepts Known :
Floor planning & Parasitic Extraction (SDF & PDEF)
Static Timing Analysis
Synthesis Case Study
Test Concepts & Methodology.
Computer Skills : VHDL,Verilog
Tools Used : Model Tech V-system Simulator ( VHDL & Verilog),
Veriwell Simulation Tool,Active VHDL tool kit,
Cypress WARP synthesis tool, Symplify.
Editors : Vi,Emacs.
Systems : MS-DOS,MS-Windows 95,Windows NT, Linux.
Fatherís Name : M.Sundararaj
Marital Status : Unmarried
Passport Number : A6518703.