In Reply to: Re: Looking for Job in VLSI / ASIC posted by Himanshu Dwivedi on 04/01/03 at 10:50 AM:
This is in reference to your advertisement for a suitable position for a Hardware Engineer. I have three years of comprehensive experience as a Designer, Implementer and Test Engineer for ASIC and FPGA based designs for applications including Digital Signal Processing using various industry standard tools and programming environments.
Currently I am working as a Design Engineer in Trident Techlabs Private Ltd. I am also pursuing part time Masters degree in Electrical Engineering with specialization in Digital Signal Processing from Delhi College of Engineering.
I have worked on a wide range of projects in VLSI System Design, ASIC Design, ASIC Verification, Full Custom FPGA Design, Assembly coding for Micro Controller & DSP’s and DSP Algorithm Design.
I am experienced with CAD tools like Cadence, Synopsys, Synplicity, Mentor Graphics, Spice,Altera, Aldec, Matlab and Texas Instruments’ DSP Processors. I am currently also doing research in areas of DSP (Control System Application) and Image Processing under Dr. A.K Agrawala (IIT Delhi). Though I have graduated in Electrical Engineering, I have zealously pursued electronics projects as my hobby and interest. I have tried to bridge the foundations of electrical and electronics subjects to generate industrial applications of electrical systems harnessing the computing era and practical electronics. It has been a continuous approach to inquire and learn any prospective technologies outside my field of work.
Please find my latest resume attached for your kind perusal.
With sincere regards,
Mohd. Mahfooz Alam,
Name : Mohd. Mahfooz Alam
Areas of Expertise : VLSI ,Digital Signal Processing
System Platform : Windows,Linux
Languages : C, C++, VHDL, Verilog ,Handel C
EDA Tools : Cadence, Synopsys, Synplicity, Mentor Graphics , Aldec, Xilinx, Matlab
M.E Control & Instrumentation From Delhi College of Engineering.
B.E. Electrical with 71% Aggregate from Rajeev Gandhi Technical University, Bhopal.
(1996 to 2000).
Experience: Three-year working Experience (July 2000 to Till date)
Working as a Design Engineer in Trident Techlabs Pvt. Ltd. New Delhi
Video Tracking based Face Recognition System. Started from May 2003
Role : Team Leader
Team Size : Four Member
I) Controllers for Power Electronic Devices conversion of the available system into FPGA.
Role : Member
Team Size : Three Member
EDA : Verilog XL, Synplicity 5.1, Xilinx ISE
Device : XC4013XLA-07PQ84
Job Responsibility Customer Duration : :: Accomplished Block level design, development and debugging, including micro architecture, RTL coding, static timing analysis, and block level documentation for a major encryption project. Developed test bench for design verification. Forbe Marshall Pvt.Ltd November 2000 to January 2001
II) IP Core Development of 8255
The core is developed for a consultant from California for California University
Role : Member
Team Size : Two Members
EDA : Active HDL, Synplicity, Altera Tool kit
Language : Verilog
Job Responsibility : Implemented, synthesized and completed timing verification of IP Core 8255 in Verilog RTL on various design-for-test (DFT) techniques, targeting Altera Flex 10k FPGA’s
Customer Duration : : TEK Consultant from California (USA) February 2001 to May 2001
III) Digital PID Controllers for DC Servo Motor, Robotics Control Application
Role : Member
Team Size : Four Member
EDA : Verilog XL, Matlab, Synplicity ,Xilinx foundation series
Job Responsibility : Designed, implemented and P, I, D constant calculation unit for PID Controller scheme in C, MATLAB and Verilog RTL. Assisted debugging in the lab at chip/board level.
Customer Duration : : DRDO(INMAS) Delhi September 2001 to January 2002
IV) Image compression using Discrete Wavelet Transform Algorithm, implemented on FPGA.
Role : Project Leader
Team Size : Four Members
EDA : Modelsim, Matlab, Synplicity,XilinxISE
Language : VHDL, Verilog
Job Responsibility : Implemented, synthesized and completed timing verification of Haar Wavelet Transform Algorithm in Verilog RTL & VHDL and targeting Xilinx XCV1000e FPGA’s Completed a study on the Image Parameter and Verify result of Algorithm using scheme in C, Matlab.
Customer Duration : : BARC Delhi March 2002 to September 2002
Summary of other Projects:
Designed and tested various digital subsystems using the above cell library as basic building blocks in the designs (Layout, Extraction & Synthesis).
Implemented and fabricated a CMOS 0.1 Micron Floating-Point Arithmetic logic study Layout Vs Schematic strategy. Fabrication of the chip was done at MOSIS to study and to familiarize with the layout and tape out issues concerning digital IC design.
Implemented and tested 89C51 Micro Controller Development kit for Graphical LCD & Temperature Control Process using Assembly Language Assisted debugging in the lab at chip/board level.
1. . Design ASIC for EIGHT BIT SIMPLE PROCESSOR
Father’s Name : Shri. M.A.Moquit
Languages Known : Hindi, English
Passport No. : A8043059
Date of Birth : 13th May, 1978
E-mail : firstname.lastname@example.org
Permanent Address : 82, Idgah Mohalla, Farid Nagar Bhilai. (Chatisgraha) 490023
Phone : 0788-393099
Present address : C/o Vipin vats,C-208, Vikashpuri New Delhi
Mobile : 01132363746
Place: Delhi M.Alam