HEre is the brief summary of my experince.
* More than TWO Years exposure to ASIC designs.
Skills: RTL coding using Verilog & VHDL,
RTL Verification for ASIC/FPGA Designs,
Scripting using Perl,
Digital logic Designing,
Multi million gates Full Chip (SoC)Verification.
Tools : NC verilog, Verilog XL from Cadence,
Synplify from Synplicity,
Xilinx Design Manager,
Bug Tracking tool,
CVS (concurrent version system),
RCS(Revision Control System).
* Protocols known
- Ethernet(XGMAC), RPR, SRP, SONET, GFP, HDLC, PCI and VCI Bus.
Should You be pleased Enough to grant me an
opportunity to know the date of an interview.