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Subject: VLSI - 2 years of exp(VHDL,Verilog HDL, FPGA, ASIC, C,C++)

Date: 06/13/03 at 2:24 AM
Posted by: J.Sudhir
E-mail: jumjur_sudhir@yahoo.co.in
Message Posted:

J.SUDHIR
Jumjur_sudhir@yahoo.co.in
Phone No: 91-8455-240014

PROFESSIONAL SUMMARY

Over 2 years of experience in Design, Development and Verification of Various Hardware Designs.
Hands on experience with technologies such as VHDL, Verilog HDL, FPGA & ASIC.
Involved in Development of RISC Processors, Digital signal Processors and Micro-controllers.
Exposure to FPGA Based Designs.
Knowledge of C, C++ & 8085 Assembly Language Programming.
Worked on full life cycle of Projects, from reviews of requirements and designs, through the
development and testing process to implementation.
Excellent communication and Inter-personnel skills. Exceptional ability to master new concepts.

OBJECTIVE

A challenging professional position that gives me scope to apply my knowledge and skills, and to
be part of a team that dynamically works towards the growth of the organization.

EXPERIENCE SUMMARY

Working as a Design Engineer In CSRDC-CSRL, Hyderabad since Jan 2001.

ACADAMIC QUALIFICATION

Bachelor Degree in Electronics & Communication Engineering from Velammal Engineering College,
University of Madras, Chennai (Oct -2000).

TECHNICAL SKILLS

Hardware Description Language : VHDL, Verilog HDL
Assembly Language : 8085
Software Language : C, C++
Operating System : MS Dos, Windows 95/98/2000
Tools : Xilinx 4.2 I Synthesizer & Modelsim Simulator
Core Skills : Digital Design Aspects, Advanced Digital Design,
FPGA & CPLD Architecture (Xilinx), CMOS VLSI Design.

PROJECT EXPERIENCE


I. Stand Alone CAN Controller Feb 2003 - Till Date
Team Size : Four
Environment: Verilog, Xilinx Foundation series 4.2I, Model-sim, Windows NT.

The CAN Controller designed for the Bit Rate up to 1Mbits/sec.It has a extra features like Error
counters with read/write access, Programmable error warning limit, Acceptance filter extension
and the single shot transmission. The architecture of this CAN controller consists of an
Interface Management Logic, Transmit Buffer, Receive Buffer with a Bit Stream Processor and
an upgraded Acceptance Filter with an Bit Timing logic. This is used within automotive and
general Industrial environment.

Responsibilities:
Coding, writing test-bench with test cases and simulating the code.
Synthesized above design and did place and route using Xilinx foundation series.


II. Digital Signal Processor (TM 320). July 2002 - Jan2003.
Team Size: Five
Environment: VHDL, Xilinx Foundation series 4.2 I, Model-sim, Windows NT.

The TM 320 Digital signal processor has a high-speed performance with very flexible instruction
set and it is cost effective. It has the advantages of performing faster algorithms and for
optimized high-level language operation. The architecture of TM 320 consists of On-chip data RAM,
On-chip ROM, parallel and serial ports, Hardware timer and Parallel Logic Unit for higher
performance. This is used mainly for differentiating signal interference and various operations,
which are useful in Ultrasound equipment, Motor control & Speech synthesis.

Responsibilities:
Coding, writing test-bench with test cases and simulating the code.
Synthesized above design and did place and route using Xilinx foundation series.


III. Veri RISC CPU. March 2002 - June 2002.
Team Size: Four
Environment: Verilog , Xilinx Foundation series 4.2 I, Model-sim, Windows NT.

The objective of this project is to create a RISC CPU, which has an instruction set of eight and
can do the multiple operations. This Veri RISC CPU consists of an accumulator, memory, program
counter, ALU, instruction register, clock generator and a control logic. The ALU gets the
operands from accumulator and memory. The result from the ALU is stored back in the accumulator
or in memory. The program counter provides the address in memory of the next instruction.
Instructions are fetched from memory and stored in the instruction register. The control logic
provides the proper sequencing of the system.

Responsibilities:
Coding, writing test-bench with test cases and simulating the code.
Synthesized above design and did place and route using Xilinx foundation series.


III. 8 Bit Micro-Controller. Sep 2001 - Feb 2002.
Team Size: Six
Environment: Verilog , Xilinx Foundation series 4.2I, Model-sim, Windows NT.

This 8-bit Micro-controller has a high performance with 4K bytes of Programmable ROM. This has a
instruction set which is compatible with the industry standard MCS-51. This provides a highly
flexible and cost effective solution to many embedded control applications. The architecture of
this micro-controller consists of 4k bytes of ROM, 128 bytes of RAM, 32 I/O lines, two 16-bit
timer/counter, a five vector two-level interrupt architecture and supports two software
selectable power saving modes. The idle mode stops the CPU while allowing the RAM, timer/counter,
serial port and interrupt system to continue functioning. The power down mode saves the RAM
contents but freezes the oscillator disabling all other chip functions.

Responsibilities
Coding, writing test-bench with test cases and simulating the code.
Synthesized above design and did place and route using Xilinx foundation series.


IV. Universal Synchronous & Asynchronous Receiver. Apr 2001 - Aug 2001.
Team Size: Four.
Environment: VHDL, Xilinx Foundation series 4.2 I, Model-sim, Windows NT.

USART is basically a serial data communication-interfacing device. It is used in conjunction with
the main processor to aid it in transferring data serially on a single line, which is otherwise
in a parallel format. It is a double-buffered programmable chip designed for synchronous and
asynchronous serial data communication. The chip has five sections: Read/Write Control Logic,
Transmitter, Receiver, Data Bus Buffer, and Modem Control.


Responsibilities:
Coding, writing test-bench with test cases and simulating the code.
Synthesized above design and did place and route using Xilinx foundation series.


PERSONAL DETAILS

Father Name : J. M. Raghu pathi Naidu
Date of Birth : 29-05-1978
Address: : L.I.G: 34, B.H.E.L, R.C.Puram, Hyderabad-500032, India.
Martial Status : Single
Language Known : English, Hindi and Telugu
Passport Details : B 0395980, valid up to 30th July 2009
Interests : Swimming, Traveling, & Reading

(J.Sudhir)


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