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Subject: Re: Need a job in Singapore/Bahrain or any country

Date: 04/22/03 at 1:08 AM
Posted by: harish malgae
E-mail: harish_malgae@rediffmail.com
Message Posted:

In Reply to: Re: Need a job in Singapore/Bahrain or any country posted by harish on 04/21/03 at 1:45 AM:

Here I am attaching my profile.

Harish Malgae
#135, RAMYA , 2nd Floor, 13th Cross,
Between 10th & 11th Main
Malleshwaram, Bangalore- 03.

Email : harish_malgae@rediffmail.com
Phone: 91-80-3369275

 EDUCATION
M.Tech. with 75% in Digital Electronics and Communication from Manipal Institute of Technology, Manipal, MAHE (deemed) University.
Bachelor of Engineering with 64% in Instrumentation Technology from Bapuji Institute of Engineering & Technology, Davanagere, affiliated to Kuvempu University, Shimoga.

Awarded with Silver medal from Institute of Engineers India, Chandigarh for the best B.E project 1998-1999.

INDUSTRY EXPERIENCE : 2 years in ASIC/FPGA front-end.

Areas of Strength : RTL design and coding using Verilog HDL.

Tool Exposure : ModelSim, Cadence NC-sim, Symplifypro


PROFESSIONAL EXPERIENCE:

Duration Employer Designation
December 2001 – Till Date United Microelectronic Solutions Ltd. Design Engineer
October 2000 – December 2001 U&I Scotty Computers Pvt. Ltd. Design Engineer

DETAILED PROJECT SUMMARY :

Organization : United Microelectronic Solutions Ltd. Bangalore.

Project # 1 : Flat Panel Display.
Team Size : 5 Engineers.
Duration : 12 months
Summary :
Today, an industrial development of information and telecommunication replaces a conventional CRT (Cathode Ray Tube) with FPD (Flat Panel Display) since CRT is much more bulky and consumes high power than FPD. The main advantages of FPD include lightweight, thinness, high resolution and low power consumption. Generally, the means of image quality enhancement are Gamma correction, Image scaling, Edge enhancement, Contrast Control, and Dithering.

Responsibilities:
 Design analysis based on the algorithm.
 Involved in architecture designing for the algorithms.
 Implementation.
 Environment: MatLab, Verilog HDL and Model-sim as simulator.


Project # 2 : Phyreg Mapper, Subaction, Arbitration gap detect & origin for 1394 bus.
Team Size : 1 Engineer.
Duration : 2 months.
Summary :
The demand for higher throughput on peripheral devices has become crucial with the growing multimedia content in PC's such as real-time color video. Digital devices generate large volumes of data, especially when high resolution and high quality results are desired. To handle the huge amounts of data from digital video and audio data streams in real time, a high-performance transport medium such as 1394 bus is needed.

Responsibilities:
 Involved in architecture design.
 Implementation.
 Environment: Verilog HDL and Model-sim as simulator.

Project # 3 : Ethernet Receiver.
Team Size : 1 Engineer.
Duration : 1 month.
Summary :
802.3 Ethernet receiver will start receiving the data according to the standard frame format, checks for the SFD (Start of Frame Delimeter-10101011) byte and will read the valid data in accordance with the length byte (two-byte) information. The received data will then be passed on to the destination once after CRC.

Responsibilities:
 Involved in architecture design.
 Implementation.
 Environment: Verilog HDL and Model-sim as simulator.


Organization : U&I Scotty Computers Pvt. Ltd., Bangalore

Project # 1 : Verilog HDL Implementation of Wavelet Transform.
Team Size : 1 Engineer.
Duration : 10 months.
Summary :
This project major objective was to design and implement an VLSI architecture that is based on 2-Dimensional Discrete Wavelet Transform to replace the most widely used 2-Dimensional Discrete Cosine Transform and to develop a generic core, for the image of generic size, which has minimal over all latency and which uses less storage space for advanced compression methods such as MPEG, JPEG, Videoconferencing etc.

Responsibilities:
 Designed and Developed VLSI architecture for wavelet transform.
 Simulated Verilog HDL code for the design
 Environment : Verilog HDL, Cadence NC-sim.


Personal Details :

Date of birth : 19th Dec 1975.
Passport : E3713746 valid till 08/12/2012.
Permanent : #1164, “Panchavati”, Taralabalu Badavane, Davangere – 577006.


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