I am M.M.Kumar from HCL Technologies Ltd,Noida,India.I have 2.5 yrs of exp in the field of VLSI/ASIC.I did my bachelors in Electronincs and communication Engg and did my P.G diplamo in VLSI.Presently I am working in DFT area.Apart from these I have sound knowledge in VHDL/Verilog,Logic design,Simulation,Synthesis and good work experience on EDA tools.
Attached is my resume for your kind consideration.
Looking forward to hear from you.
M. Marimuthu Kumar
Permanent address: Present address:
15/29,Golden Nagar. A-403,sector-19,
Bharathiar University (p.o), Noida,
Coimbatore, Uttar Pradesh-201301.
Tamil Nadu-641046 Ph:09810489993.
Ph:0422-424249 E-mail: email@example.com
Over 2 years and 1 month of professional experience in ASIC Design and Verification including 1 month of onsite experience at Coware Inc, Santa Clara, USA. Currently working as a Member Technical Staff at HCL Technologies, Noida. Apart from my industrial experience I have four months of professional training in VLSI Back-End and Front-End (VHDL, FPGA, CPLD, Simulation and Synthesis issues and static timing analysis). Experience in programming in VHDL, Verilog, CowareC (SystemC), PERL.Having good learning curve and good communication skills.
Bachelor of Engineering (E.C.E) from S.R.E.C, Coimbatore
(1996 – 2000)
Areas of Expertise
Operating Systems used
EDA Tools used
DFT/ATPG Tools used
Logic Design, Xilinx CPLD, FPGA Architectures
Bluetooth protocol, DSP.RTL coding, synthesis, simulation and verification, Front-End Design using VHDL.
UNIX, DOS, Windows 98 and Windows NT, SOLARIS
C, CowareC, Perl.
FPGA Advantage (Renoir, Modelsim, Leonardo Spectrum)
Xilinx Foundation series [F2.1]
Synplify from Synplicity
Coware N2C co-simulation tool.
Fastscan/DFT insight from Mentor Graphics
P.G Diploma in VLSI Design at Bitmapper Integration Technologies, Pune, India.
Coware certification for N2C Training, Santa Clara, USA.
Member Technical Staff HCL Technologies 10/2000 – Till Date
Title: Development of Bluetooth Baseband controller
Bluetooth is a short-range wireless protocol operating in the ISM frequency band (2.4 Ghz) intended to replace the cable(s) connecting portable and/or fixed electronic devices. The transceiver utilizes frequency hoping to reduce interference and fading. A typical Bluetooth device has a range of about 10 meters. The communication channel can support both data (asynchronous) and voice (synchronous) communications .Its key features are robustness, low complexity, low power and low cost. We were implementing the baseband specification in hardware using VHDL in the form of Bluetooth Baseband Controller.
Role: As a Team member, my contribution to the project was in the high level and detailed design of the sub blocks like CRC, FEC & HEC of both transmitter & receiver. The work involved translating the RTL specs to High–Level Design and finally coding in VHDL.
Duration: 3 months (for HCL Technologies, Noida)
Title: Distributed Arithmetic FIR Filter Soft core.
Digital filters are widely used in processing digital signals of many diverse applications, including speech processing and data communications, image and video processing etc., FIR filter is one of those digital filter in which the impulse response h (n) is non-zero for only a finite number of samples. Distributed arithmetic is a computation algorithm that performs multiplication with look –up table-based schemes. DA specifically targets the sum of products (vector dot product) computation that covers many of the important DSP filtering and frequency transforming functions.
Role: As a Team member, my contribution to the project was in defining the specs, identifying the right method for computing, freezing the technique for computing impulse response and finally coding in VHDL and to implement the design into the target FPGA.
Duration: 3 months (for HCL Technologies, Noida)
Building a PSP (Processor Support Package) for DSP16T11 digital signal processor from LG using CowareN2C Design and methodology
Coware N2C Design system is an environment for Intellectual Property (I.P) reuse and hardware/software co-design. It supports common h/w and s/w compilers and simulators, allows for parallel hardware/software co-specification, multilevel hardware/software co-simulation and hardware/software co-implementation. This Coware tool and methodology is mainly meant for System-On-Chip (S.O.C) designs.
The PSP consists of ISP, BSP, and SSP.
The ISP (Instruction set Support Package) is the processor model for use in Coware environment.
The SSP (Software Support Package) consists of the SW architecture associated with the core (Boot code, OS libraries, linker script, startup code)
The BSP (Bus Support Package) is the HW flexible/configurable architecture associated with the core. The BSP contains (Bridges, Scenarios for connecting to user HW, peripherals)
DSP16T11 is a 16-bit fixed-point digital signal processor. This is based on an advanced modified Harvard architecture that has one program memory bus and three data memory bus. It provides an ALU that has a high degree of parallelism, application specific hardware logic, and additional peripherals. DSP16T11 can be used as an ASIC library element in variety of DSP applications.
Duration: 3 months (Coware Inc, USA .1 month onsite and 2 months offshore)
The Advanced Microcontroller Bus Architecture (AMBA) specification defines an onchip communications standard for designing high-performance embedded microcontrollers.
Three distinct buses are defined within the AMBA specification:
• The Advanced High-performance Bus (AHB)
• The Advanced System Bus (ASB)
• The Advanced Peripheral Bus (APB).
As a Team member, my contribution to the project was in the high level and detailed design of the blocks like the Arbiter, Address decoders and multiplexors in AMBA AHB. The work involved translating the RTL specs to High–Level Design and finally coding in VHDL.The job also involved unit level testing of the slave device. Behavior modeling of AHB and APB bus monitor to continuously monitor all the signals and to report any violations as per AMBA spec.
Duration: (15’th Dec 2001 to May 2002)
Title: N1-SGI-ATPG (Current Project)
Conversion of existing "NEWT" RTL/netlist of N1 to equivalent ATPG ready Verilog netlist. The Verilog netlist will be used for fault grading and generating the ATPG vectors. The aim is to achieve reasonable fault coverage.
As a team member, my role to the project is to convert “NEWT” (proprietary language of the client) to equivalent Verilog netlist and to generate ATPG vectors to achieve high fault coverage. The job also includes writing perl scripts for atomizing some of the processes.
Duration: (13th May to Till date for SGI, US)
VLSI Training. Bitmapper Integration
Tech, Pvt Ltd. 07/2000 – 10/2000
1. Design Of SRAM (IC-6116) using VHDL
a. Synthesized and simulated the functionality in Xilinx's Foundation
b. Behavioral Modeling in MODELSIM 5.3c
2. Design of standard Linear Feedback Shift Register in VHDL.
Implementation of Programmable Peripheral Interfacing Device (8255) using VHDL
Department of Electronics & Communication Engineering, S.R.E.C.
Languages Used: VHDL
Interest & Activities:
Treasurer of the Association of Electronics and Communication Dept, S.R.E.C.
Member of ISTE.
Member of IEEE
Playing Cricket and listening to Music.
Won prizes in National level cultural events.