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Subject: looking for a job in physical design/p&r

Date: 03/03/03 at 1:48 AM
Posted by: sanjay kumar
E-mail: s_sugurmath@yahoo.com
Message Posted:


Email ID: s_sugurmath@yahoo.com

phone no. 9448011124

* Professional Experience :
2yrs & 3 months of industry experience of which 2 yrs in the field of VLSI Physical
design/P & R.

* Experience :
Aug - 2000 to June - 2002
Designation : Support Center Engineer - I.
Avant! Software & Development Center (India) pvt Ltd.

May- 2000 to July 2000
Designation : Graduate Apprentice.
Bharat Electronics Limited,

* Areas Of Expertise:

o Physical Design (P&R)
o Data Preparation
o Floor Planning
o Place and Route
o Timing Optimization
o Static Timing Analysis
o Layout Parasitic Extraction
o CMOS Concepts
o Layout Design (Std Cell Design)
o Perl/Tcl Script/ Scheme Programming
o Physical Verifications (LVS and DRC)
o Able to work reliably under pressure
o Sense of strong responsibility and accomplishment
o Excellent communication and inter-personal skills

Educational Qualification:
Bachelor of Engineering in Electronics and Communication,Gulbarga University, Karnataka, India.

Technical Skills:

Operating System : MS DOS, Unix, Windows 95/98,
Sun Solaris, HP-UX
Languages : C, C++, X85/86 Assembly.
Language Programming : Scheme Programming,Perl,Tcl.
Hardware Languages : VHDL, Verilog.
EDA Tools : Avant! Tools suite
Jupiter (Avant! Single pass flow)
Apollo (P&R), Milkyway, PlanetPL
Saturn ( Static Timing Analysis)
Mars rail/Mars Crosstalk,
Projects Developed

Project #1 Java Processor Chip (Avant! Single Pass Flow Design Chip)
Tools Used Planet-PL, Milkyway,Apollo/Saturn.
Client Avant! corporation, Fremont
Duration 2 months
Locatio n Avant! India,Hyderabad.
Designation Design Engineer.

Abstract :

This project was aimed to implement the Single pass flow using Planet-PL and Apollo.Place and route the hierarchical design using PlanetPL and Apollo flow.Basically this design consists of five blocks, and the flow involved Hierarchical Manipulation , Timing Budgeting, Floorplanning ,Block placement ,and wire load estimation. Each block has to be placed and routed and then the Top level cell is Placed and routed considering timing constraints and area constraints. The target environment was 0.25 um, and the passport cb25 library is used for Standard cells. Finally accomplished the project with successful target results.

Project #2 LSI Design Case
Tools used Milkyway,Apollo(p&r)
Client LSI Logics Inc, CA
Duration 2 months
Location Avant! India Hyderabad.
Position Design Engineer

Design Specification
Design size 190k std cells, 13 Macros
Main issues To meet the required Area (diesize) constraints

The main aim of this project was to reduce the Die size by 15% using Apollo/Milkyway,many different placement and routing tricks were used to get the required Die size, after going through the whole flow with many iterations using some of the avant! Placement tricks met with the required Die size. Some of the issues which found to be critical in Detail routing when using the utilization factor as 87% were proper Preroute P/G ring, placement, and removal of hotspots to make ease for routing. Finally got the DRC clean result for the 87% utilization factor.

Project#3 DalSemi Timing Bench Mark
Tools used Apollo(p&r),Saturn, starRCXT
Client Avant! Internal tool evaluation project.
Duration 1 month
Location Avant! Hyderabad, India
Position Design Engineer

Design Specification
Design size 250 K std cells ,19 macros
Process 0.25 um,5 layer.
Target place & route,timing optimization.

The project was aimed to meet the timing.The initial setup time was -61ns.The final target was to meet a setup time of -0.5ns & hold time of 0.00ns.The subtarget was not to modify the floorplan. The cells were placed using saturn in place optimisation followed by manual tuning of standard cells. Finally improved the timing by extracting the parasitics.

Project#4 Timing Testcase.

Tools used Apollo(p&r),Saturn.
Client Avant! Internal tool evaluation project.
Duration 1 month
Location Avant! Hyderabad, India
Position Design Engineer

Design Specification
Design size 13.5 K std cells
Process 0.32 um,4 layer.
Target slack of 0.15ns & a clock skew of 0.10ns.

Abstract :
The project was aimed to remove the transition & setup time violations. The target slack Was 0.15ns with a clock skew of 0.10ns. By setting some placement constraints the target was met. Finally the design was routed with drc & lvs clean.

Project#5 Diesize BenchMark

Tools used Apollo(p&r)
Client Avant! Internal tool evaluation project.
Duration 1 month
Location Avant! Hyderabad, India
Position Design Engineer

Design Specification
Design size 103 K std cells, 29 Macros.
Process 0.24 um,5 layer.

Abstract :
The main objective was to place 29 macros with 103k standard cells with in the target area of 97% utilization. This was met trying out with various macro orientations along with some placement tricks to reduce the congestion. Finally met the target with drc & lvs clean.

Passport Details :
Passport No. : A8631910
Date of Issue : 09/02/2000
Date of Expiry : 08/02/2010
Place of Issue : Bangalore.

Contact Address:
Gayatri Nagar,Mariyappana Paalya

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