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Subject: Re: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!!

Date: 11/03/03 at 6:28 AM
Posted by: Atmanand V Revankar
E-mail: atmanandvr@rediffmail.com
Message Posted:

In Reply to: Re: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!! posted by Madhaiyan.M on 09/11/03 at 1:41 AM:

Respected Sir/Madam,
I, Atmanand Revankar am an engineering graduate in Electronics & Communication.

Having completed my engineering, which was my sole goal from my wonder years, it seemed that my objective was finally achieved. However, seeing the explosive growth in this arena and the magnitude of new products coming out by the minute, I realized that there is still a long way to go. Continuing, in this endeavor, I took up a career in R&D with LRDE, DRDO one of the premier R&D institutes of India.

Having worked here for 26 months I would now want to explore the different areas, where my knowledge heightened by my dreams would take me.

Offering my complete resources, I submit my resume for your kind perusal.

Thanking You,

Atmanand Revankar


Atmanand.V.Revankar
SH-5A/99, DRDO TOWNSHIP,
PHASE-II, KAGGADASPURA
Bangalore-560093
Mobile: 9886147096
Office: 080-5243505
mailto: atmanandvr@rediffmail.com

Summary
A Electronics & Communication Engineer, with over 26 months of R&D experience, presently working as JRF (Junior Research Fellow) for LRDE, DRDO Bangalore. Work experience involves analysis, design, development, implementation and verification of VLSI systems such as FPGAs & CPLDs (RTL Coding, Simulation & Synthesis of FPGAs, Static timing Analysis, Test Bench Development, Verification).

Career Objective
To pursue challenging career which enhances both professional and personal growth.

Qualification
* B.E., Electronics & Communication from K.L.E. College of Engg & Tech, Karnataka University, Dharwad with an aggregate of 70.5%.
* P.U.C from Govt Arts & Science College, Karwar with 74.67%.
* S.S.L.C from Hindu High School, Karwar with 84.57%.

Training Programs Attended
* Undergone PG-Diploma Course Training in the VLSI Design at Sandeepani School of VLSI DESIGN, CG-CoreEl Programmable Solutions Pvt.Ltd. Bangalore.
Duration: 4 Months (June 2001- Sep 2001).
* Certificate Course in the VLSI Design (FPGA Backend) at Bitmapper Technologies.
Duration: 4 days.

Technical Skills
Languages : C,Assembly.
HDLs : VHDL,Verilog.
Tools : Modelsim Simulation Tool, Leonardo Spectrum Synthesis Tool, Xilinx
ISE 5.1i, FPGA Express from Synopsys, Synplify & Synplify Pro
Synthesis Tool, Atmel System Designer 2.1, Altera Quartus 2.0, FPGA
ADV 5.2, IAR Embedded Workbench development tool, Sharc Tools.
Operating System : Win 98/ME/XP, Win 2000, Sun Solaris.
Knowledge of : DSP Domain, Digital CMOS VLSI, Good Exposure to FPGAs &
CPLDs from XILINX, ALTERA, ATMEL. Micro-controllers from INTEL, ATMEL.
Proficient in: VHDL programming.
Expousure to Different Measuring Instruments like LOGIC ANALYSER, SPECTRUM ANALYSER, OSCILLOSCOPES, SIGNAL GENERATORS.
Strengths
Good Analytical & Problem solving Skills, Responsible with good Communication, Fast Learner, Persistent & Adaptive.
Relevant Work Experience and Accomplishments
* LRDE, DRDO Bangalore (Feb2002-Todate)

Designation Junior Research Fellow
Work involves design, development and implementation of Embedded Systems (8 & 16-bit Microcontrollers) & VLSI Systems. Simulation & Synthesis methodology of FPGAs, Static timing Analysis, Verification & Designing of Prototype Boards.
* LRDE, DRDO Bangalore (Oct2001-Jan2002)
Designation - Contract Engineer.
Work involved design, development and implementation of Digital Systems using VLSI Technology, VHDL based RTL designs, Synthesis, Timing Analysis, Placement & Routing of FPGAs.

Projects

Company Name LRDE, DRDO Bangalore.
Duration
Project Name Nov2002 To date
DISTRIBUTED BEAM STEERING CONTROLLER FOR ACTIVE
APERTURE RADAR ARRAY
Project Description
Active Aperture array consists of large number of antenna elements each integrated with a T/R module. In a active array T/R modules are the key elements, the size, weight and cost of these has greater influences in Active Array RADAR development. The T/R module employs a FPGA based controller circuitry for generating the required amplitude & phase weights for side-lobe control and electronic scanning of the array. These T/R module controllers are to be integrated with beam steering controller for command control & data distribution.
Responsibilities
* Designing & Coding.
* Design of Prototype Board.
* Testing of each module using Xilinx FPGAs & Atmel FPSLIC.
Environment VHDL, Xilinx Tools, Atmel System Designer.


Company Name LRDE, DRDO Bangalore
Project Name

Duration Programming of AD-9854 Analog Devices DIRECT DIGITAL SYNTHESIZER (DDS) Evaluation Board.
June 2003 To date
Project Description
Digital synthesizer is a highly integrated device that uses the advanced DDS technology. When referenced to accurate clock source, the AD9854 generates highly stable, frequency-phase-amplitude-programmable sine and cosine outputs that can be used as an agile L.O. in communications, Radar etc. This has to be programmed for the desired functionality in the current project. This can be done using either FPGAs or Micro-controllers.
Responsibilities
* Designing and Coding.
* Testing using Xilinx FPGAs.
Environment VHDL, Xilinx Tools
Company Name LRDE, DRDO Bangalore
Project Name Timing Card for the RADAR Array
Project Description
Timing card provides the necessary timing signals required for the Array Operation. This generates P.R.T (reference) timing signal (T/R pulse), with programmable Pulse widths & PRTs. The Timing card is designed using Xilinx FPGAs.
Responsibilities
* Designing and Coding.
* Testing using Xilinx FPGAs.
Environment VHDL, Xilinx Tools

Project Training Project.
Duration
Team size 2 months.
3
Project Name Hardware implementation of a Multiplier-Less N-Tap FIR Filter.
Abstract:
Implementation of FIR digital filters for ASIC/FPGA can take several approaches. In this project we implement a n-tap FIR filter for both ASIC/FPGA. The methods employed come under the following categories.
a) Direct implementation with VHDL as HDL.
b) Implementation using Array Multipliers.
c) Multiplier less implementation using Look Up Tables (LUTs).
A comparative study of the three multipliers for hardware, performance & power is also being carried out.

Project Name Creation of a virtual system for parallel execution.
Abstract:
The advancement of computer networking technology has opened wide bandwidth for optimum use of computers. Time is an important factor in this fast action era. Hence we are attempting to create a programming environment where a number of computers can be treated as a single resource, when linked together via a communication network, which enables the user to write parallel programs that run across distributed computers simultaneously. The virtual machine is enabled through a client-server model.
This project was being implemented in Java and RMI feature of Java.
K.S.C.S.T Bangalore sponsored this project.
Environment Java 2.0

Personal Details
Date of birth: 22nd August 1978.
Sex: Male.
Marital Status: Unmarried.
Passport No: E 1524698
Languages known: English, Kannada, Hindi, Marathi and Konkani.
Other Interests: Music & Reading.
Permanent Address: S/o Mr. V. A. Revankar,
Atmaram Niwas,
Post: Nandanagdda,
Baad, Karwar,
Karnataka.

Place: Bangalore
Date: (Atmanand .V. Revankar)


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