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Subject: Re: Hardware VLSI/ Memory Design/ ASIC Engineer in BAY AREA Full Time/ Contract position

Date: 10/21/03 at 4:51 AM
Posted by: Ashish Kalawar
E-mail: ashishkalawar@yahoo.com
Message Posted:

In Reply to: Hardware VLSI/ Memory Design/ ASIC Engineer in BAY AREA Full Time/ Contract position posted by Hemant Dandekar on 10/07/02 at 1:55 AM:

C/o.Shri.Vijayrao L. Kalawar
147,Ayodhya nagar,
Near saimandir(Maharashtra)
Phone No.# 9818285509 / 91-0712-2759086
Passport No.: E0941374
Email: ashishkalawar@indiatimes.com

OBJECTIVE: Seeking a position to utilize my skills and abilities in the Industry that offers Professional growth while being resourceful, innovative and flexible.

-Ten-Month Design Experience in ArmyResearchDevelopmentEstablishment,
Pune (10th Sept.2001 to 15th May 2002)
-Currently working as an Application/Design Engineer in Trident Techlabs Pvt.Ltd., New Delhi.

- Executed Advance diploma in VLSI design at Pune university
- Expertise in Digital design &Analog design& mixed mode.
- ASIC/FPGA/CPLD design flow awareness
- Experience in HDL coding .
- Hands on experience RTL coding, Verification, timing Analysis and test ,
Development and implementation.


Languages : VHDL, Verilog, C, Microcontroller 8051, ALP.
CAE Tools : ActiveHDL5.2/6.1 , ModelSim , Pspice, DiALS(Optical Simulator)
Xilinx Foundation Series 4.1/Webpack4.2,Riviera(ASIC verification),
Leonardo Spectrum, EWB7.1, SynplifyPro7.2, Simulator8085/8086,
Ultiboard7.1(PCB design),PSIM6.0
Installation : Network license for EDA software(ActiveHDL,SynplifyPro).
Operating Systems : MS-Windows 9x/2k/NT/XP
Technology : Xilinx FPGA/CPLD (XC5202PC84/XCS02PC84/XCS05TQ144/XC9572PC84)


07/01 Diploma in CAD-VLSI design, Pune University,
1997 - 2001 Bachelor of Engineering ( BE) in Electronics, Nagpur University ( 61%)
1995 - 1997 XI-XII, Maharashtra Board (68.78%)
1995 X,Maharashtra Board (74%)

1) Project (VLSI):

- FPGA Based Processor Design For Mine Ejection System
Sponsored By Armament Research & Development Establishment, Pune.
The processor is designed for operating mechanical system for mine ejection.
Tools Used: Xilinx4.1 ; Device Used: XC9572Pc84

- FPGA Based Timer For Safety and Arming Mechanism
Sponsored By Armament Research & Development Establishment, Pune.
Timing parameters are settable at any change of development and even at last minute change in field. GUI is made in C language.
Tools Used: Xilinx4.1 ; Device Used: XC9572Pc84

- FPGA Based DSP Unit for Radio Proximity Fuse.
This project is a DSP application to be implemented in a FPGA . The aim of the project is to use Correlation and FFT techniques to work upon the received bit sequence, to determine the relative location of the target, and accordingly activate the fuse of the guided missile. The project is targeted on a Xilinx Spartan device, using VHDL for describing the functionality of the system.

-Simulator 8086 development

2) B.E. Project:

- Wireless Programmable Control Unit Using PC.
Wireless programmable control unit using PC is consisting of FM communication system, pc, and 8085 microprocessor, output device that is to be controlled. Software is made in ‘C’ language.

- PCB Design For Sound Scanner Circuit.

Extracurricular Activities:

1) Participated In 0ne day work-shop on “ADVANCES IN MICROELECTRONICS"
organized by IEEE Bombay and Dept Of Elec. Science, University Of Pune.
2) Participated In Two day's National Seminar On "DSP-VLSI Design &Applications"
organized by Dept Of Elec. Science, University Of Pune.
3) Won the prizes in various drawing competitions .
4) Participation in cultural activities at school and college levels.

Personal Details:
Fathers Name: Shri.Vijayrao L. Kalawar
Sex: -Male
Reference: - Mr.Chandrashekhar Gampawar (Sr. Engg. In PHILIPS, Pune)
Mail Id: cvgampawar@yahoo.com
Phone No.:020-5386828®
Place of work: Any where in India/Abroad.

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