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Subject: Re: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!!

Date: 09/11/03 at 1:41 AM
Posted by: Madhaiyan.M
E-mail: madhu_kemp@yahoo.com
Message Posted:

In Reply to: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!! posted by Rupa on 08/20/02 at 2:18 AM:

CURRICULUM VITAE

Madhaiyan.M
4/3,Pavan Complex
VRN Lane,S P Road
Bangalore-2.
E-mail: madhu_kemp@yahoo.com
Contact No: 091-080-2239599
Objective
To work with a progressive organization in which I can contribute my technical Skills and my experience to enhance my own productivity at the same time achieving the organization objective with the attribute of time, quality and discipline
Experience:
· 2+ Years of experience in Design (Verilog, VHDL), Verification & Synthesis
ü Working as a Design Engineer in Integrated Business Software & Development, Bangalore from July 2002 to till date.
ü Worked as a Design Engineer in Greenrose Computer Services Pvt. Ltd., Bangalore from January 2001 to July 2002.
Technical Skills:
· Hardware Skills : Digital Design, CMOS Design,FPGA, ASIC
· HDLs : Verilog, VHDL.
· Worked on Tools : Xilinx4.1i, ModulSim5.5b, FPGA Express, ALDEC
· Software Skills : C
· Assembly Languages : Intel 8085, Micro controller 8051
· Domain : Digital Signal Processing
Project Details
Project #1
· Project title : DESIGN AND IMPLEMENTATION OF MPEG-4 VIDEO COMPRESSION (DSP)
· Role : Design and Implementation of DC T/IDCT block Implemented in : Xilinx Integrated Software Environment(ISE)
· HDL : VHDL
· Simulation Tool : ModelSim XE 5.5b.
· Synthesis Tool : FPGA Express Xilinx Edition 3.6.0.
· Abstract : This project is a modest effort in the field of image processing, to implement the processor which processes the image data sent by the encoder using the most efficient, image independent mathematical tool(DCT/IDCT).The module gives the most efficient decoded data with maximum error of one. The key feature of this module is the efficient usage of pipelined architecture. The basic application areas are Video Telephony, videoconference, High Definition Televisions etc.
Project #2
· Project title : IIR Filter (DSP)
· Role : Design and Implementation of IIR
· Implemented in : Xilinx Integrated Software Environment(ISE)
· HDL : Verilog
· Simulation Tool : ModelSim XE 5.5b.
· Synthesis Tool : FPGA Express Xilinx Edition 3.6.0.
· Abstract : The term filter is commonly used to describe a device that discriminates according to some attributes of the objects applied at its input, what passes through it. A linear time invariant system can perform a type of discrimination of filtering among the various frequency components at its input. the nature of filtering action of this filter is determined by frequency response characteristics H(W).A Linear time invariant system modifies the input signal spectrum X(W) according to its frequency response (W) to yield an output signal with spectrum Y(W).
Project #3
· Project title : DESIGN AND IMPLEMENTATION OF FFT ALGORITHM (DSP)
· Role : Design and Implementation of FFT processor
· Implemented in : Xilinx Integrated Software Environment(ISE)
· HDL : VHDL
· Simulation Tool : ModelSim XE 5.5b.
· Synthesis Tool : FPGA Express Xilinx Edition 3.6.0.
· Abstract : Frequency analysis of discrete time signals is usually and most conveniently performed on a digital signal processor. FFT involves operations on a block of data, which by necessity must be limited. In size due to limited memory of a digital computer, a long sequence must be segmented to fixed size blocks prior to processing.
To perform frequency analysis on a discrete time signal {x (n)}, we convert the Time Domain sequence into Frequency Domain representation. Such a representation is given by the Fourier Transform X (w) of the sequence {x (n)}. However, X (w) is a continuous function of frequency and therefore, it is not a computationally convenient representation of the sequence {x (n)}. Discrete Fourier transform (DFT) is a frequency domain representation of a sequence {x (n)} by samples of its spectrum X (w).
Project #4:
· Project title : I2C CONTROLLER
· Role : Design and Implementation
· Implemented in : Xilinx Integrated Software Environment(ISE)
· HDL : VHDL
· Simulation Too : ModelSim XE 5.5b.
· Synthesis Tool : FPGA Express Xilinx Edition 3.6.0.
· Abstract : A system using a serial communications protocol passes messages to/and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count. This also helps to maximize hardware efficiency and circuit simplicity. One such protocol, which uses this communication process, is the I2C protocol. This is useful in connecting different devices, which supports this protocol internal to an IC. For a device to support this protocol there should be one controller, which is to be connected with the device. This is the I2C controller.
Accomplishment: Voice Operated system for blind people
(Sponsored by Tamilnadu State Council for Science and Technology)
Abstract: This project is aimed at developing voice-operated systems to help everyone’s specifically the blind people to get into I.T revolution. Generally voice operated systems are used where hand-free, and eyes-free use of devices is of premier importance and wherever faster access is needed
Educational Qualifications
· B.E (Electronics & Communication Engineering) from IRT Tech College (Reputed college), Erode (Bharathiyar University) 2001.
Personal Details
· Date of Birth : 25th MAY 1979.
· Marital Status : Single.
· Permanent Address : S/O Munuswamy,A.Jettihalli Post
Dharmapuri District


Reference: Mr.Sunil.PM,
Ph: 9845369646


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