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Subject: Re: Looking for job in VLSI/ASIC design

Date: 06/06/03 at 6:02 AM
Posted by: kamalakannan
E-mail: kamal_eee@rediff.com,rush2kamal@yahoo.com
Message Posted:

In Reply to: Re: Looking for job in VLSI/ASIC design posted by Ajaya Kumar on 01/06/03 at 3:04 AM:

D.Kamalakannan
Phone :+91-4298-223717
Email : kamal_eee@rediff.com

Summary

To ascend from my present carrier as a Design Engineer, I seek an atmosphere of far more reaching challenges and satisfying opportunities, to utilize my knowledge and talents acquired in logic design with high level descriptions (VHDL/Verilog) and my creativity to achieve excellence in my profession.
Three years of wide experience in VLSI Digital circuits Design using simulation and synthesis tools, Electronic Design and automation (EDA) tools and Design Manager

Technical Skills:
High-Level Languages : VHDL, Verilog-HDL
Programming Languages : C
Operating System : Windows 95/98/NT/2000

Specialized EDA Tools:
Simulation Tool :Modelsim SE/EE 5.4d (Mixed simulation in
VHDL and Verilog)
Synthesis Tool :Leonardo Spectrum (Exemplar Logic), Altera
MaxPlus II, FPGA Express (Synopsys)
Place & Route Tool :Design Manager (Alliance Series)
Technology :FPGA (Xilinx, Altera, Actel)
Knowledge Base :PCI, JTAG, CMOS, VITAL Simulation,
BlueTooth

Personal Details :

Date of Birth :28th Augest1976
Age :26 years
Sex :Male
Marital Status :Single
Nationality :Indian
Contact:E-mail :kamal_eee@rediff.com,rush2kamal@yahoo.com
Residential No : +91 (0)4298-223717


Education
Bachelor of Engineering (Electrical & Electronics) - First Class

Kongu Engineering College,Erode , Bharathiar University, Coimbatore (1995 - 1999 )

Professional Experience:

Worked as a Design Engineer at VDesign Pvt. Ltd. from OCT1999 to Nov 2002, a French based company in Pondicherry. The company is a 100 percent export oriented unit and executes many prestigious projects in VLSI.

At present working as a lecturer in SRM Engg. College (ECE- Handling VLSI paper )

Client :VDesign Pvt. Ltd,
Project Title :SONET .
Project Description :

The input is a 32-bit data at 33 MHz frequency. The datas are converted into base format of synchronous STS-1 signal and stored in the Framer. The Framer can store 810 bytes, 36 bytes of overhead and the remaining for payload. A Pointer is used to indicate location of data, to avoid delays and loss of data associated.
Transmission is carried out at a bit rate of 2.5 Gbps.

My Role:

 Defined the top-level module and identified the sub-modules necessary to build the top-level module.
 Designed of various synthesizable core modules are written in VHDL.
 Verified through simulation using Modelsim and synthesized using Leonardo Spectrum.


Client :VDesign Pvt. Ltd,
Project Title : CODEC for Bluetooth AND Bluetooth packet generation


Project Description:

Packet Generation is one of the module developed for Bluetooth project, in which data are sent through the packets. Two type of packets are developed, SCO is Synchronous connection Oriented, is used to transmit time - bounded signal like voice signal, and ACL is Asynchronous connection Less, is used for common signal data. Each packet contains Access code, Header and Payload are generated according to the Bluetooth Specification.

CODEC is the basic unit of digital transmission network, which contains Encoder and Decoder. Bluetooth specifies three different coding techniques: Log PCM coding using A-Law, -Law and CVSD (Continuous Variable Slope Delta Modulation). It is designed according to ITU-T, recommendation G.711.

My Role:

 Designing of various core modules such as Encoder and Decoder.
 All modules are synthesizable (Mostly RTL) and written in VHDL.
 Verification of the design functionality through simulation using Modelsim and
synthesized using Leonardo Spectrum.

Client :VDesign Pvt. Ltd,
Project Title :PCI (Peripheral Component Interface)


Project Description:

PCI is an intelligent, high performance interface that enables system designers to integrate a variety of functions. Its a 32-bit controller which operates at 33MHz clock designed to interface with memory-mapped devices. The project is to make PCI based floating point frequency synthesizer. The desired output frequency is entered via keyboard. The PCI bus receives, process the input data and produce corresponding output.

My Role:

 Designed all the PCI modules according to PCI bus specification, version 2.0.
 The modules are verified for its functionality by utilizing different test vectors.
 Synthesized the whole project using Leonardo Spectrum and mapped using Design Manager for the Xilinx FPGA.

Client :VDesign Pvt. Ltd,
Title :Content Addressable Memory (CAM)


Project Description:

CAM is the fastest search result provider. It is used as a translation table for Virtual Path Identifier (VPI) and Virtual Channel Identifier (VCI) in ATM switching network, which is a multiphase data communicator with features of TDM and Packet switching. In CAM VPI/VCI values are compared within a clock cycle by using Lookup tables. Then RAM block, which is combined with CAM, is activated by a match signal coming out of CAM block. Then new value of VPI/VCI is obtained from RAM

My Role:

 Designed all the CAM modules according to specification
 The modules are verified for its functionality by utilizing different test vectors.
 Synthesized the whole project using Leonardo Spectrum and mapped using Design Manager for the Xilinx FPGA.

Client : VDesign Pvt. Ltd,
Project Title : Embedded Controller

Project Description:

A 4-bit Embedded Controller is used for controlling of voice synthesis processor TMS5100. The various programs are stored in ROM for controlling the voice processor. The programs are designed to make the voice synthesis system speak various phrases.


My Role:

 Designed the modules of the Embedded Controller in VHDL.
 Verified the design functionality using Modelsim Simulator, synthesized using Leonardo Spectrum and mapped using design Manager for the Xilinx FPGA.

Client : VDesign Pvt. Ltd,
Title : Asynchronous Transmitter and Receiver


Description

UART transmits the data at a rate of 100 MHz and a receiver, which receives the data at a rate of 2 MHz, and the clock frequency used is 16 MHz.

My Role:

 Designed the modules of the Asynchronous Transmitter and Receiver in VHDL.
 Verified the design functionality using Modelsim Simulator, synthesized using Leonardo Spectrum and mapped using design Manager for the Xilinx FPGA.



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