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Subject: Re: Looking for job in VLSI/ASIC design

Date: 05/06/03 at 3:08 AM
Posted by: Senthilvadivu
E-mail: sen_vadivu@yahoo.com
Message Posted:

In Reply to: Re: Looking for job in VLSI/ASIC design posted by Ajaya Kumar on 01/06/03 at 3:04 AM:


Annai Indira Gandhi working women?s hostel
28,Ayyasamy Street, Nehru Nagar, Chromepet
Chennai-600 044. INDIA.
Phone: 044-22235048
Email: sen_vadivu@yahoo.com


To become a member of an invincible team where my talents will be used to the fullest extent.

Project Associate,
AU-KBC Research center for Internet and telecommunication Technologies,
Dept .of Electronics, Madras Institute of Technology, ANNA University,
Chennai, India.
Duration: From March 2001 to till date.

Area of Work:
Exposure to design and development of IP cores for the communication, image processing and related signal-processing applications.


Ě VHDL, Verilog, C.
. Assembly Language Programming for Microcontrollers, RTOS- ÁC/OS, QNX
. Model Sim SE/EE 5.4d.
. Lenoardo Spectrum for synthesis.
. Workview Office VIEWlogic Schematic capture tool.
. Synplicity.
. MATLab 6.0.
. Well versed in PHY layer for WLAN standards (IEEE 802.11a, 802.11b, 802.11g, 802.15, 802.16,HIPERLAN-2) and video codec design for MPEG-4 and JPEG-2000 standards.


M.E (Electronics) at MIT, ANNA University with a GPA of 7.66 (First Class 99-01).

B.E. (Electrical and Electronics Engg.) at Amrita Institute Of Technology And Science affiliated to Bharathiar University with 74.56 % (First Class, 95-99).
GATE-1999 Score - 80 percentile.


VLSI System Design for digital communication, digital Image Processing and digital signal processing applications.


ĚHave attended 13th International Conference on VLSI Design conducted by VLSI Society of India. (The theme of the conference was Wireless and Digital Imaging in the millenium).
ĚHave attended a one day tutorial on Video Information System conducted by IEEE Bangalore section, as part of the International Conference On Communication, Control and Signal Processing in the next millenium.


1.VLSI implementation of QAM-256 transceiver.

QAM transmission has a high spectral efficiency and high system capacity as compared with other modulation schemes such as BPSK, QPSK and M-PSK. The QAM scheme plays a dominant role in Broadband Data Communications and Cable Modems. So, VLSI implementation of QAM-256 modem is attempted by a group of three members. This was a Sponsored project and the client was COMIT Systems Inc US. The important modules in the QAM transceiver are:
1. Transmit and receive Square Root Nyquist filter: Four ten tap and two twenty-tap multiplier less filters were implemented in transmitter and receiver respectively.
2. The receiver constitutes Feed forward and a decision feedback equalizer. Equalization is done by two twenty tap adaptive filters and the adoption algorithm used is LMS.
3. Robust time and frequency synchronization techniques were implemented.
4. The complete integration of the transceiver (which constitutes few other modules like mapper and demapper) was targeted for Xilinx Virtex FPGA.

My role in this project:
1.The architecture for the various modules was frozen.
2.The VLSI implementation of Synchronization modules and the LMS algorithm and complete integration were carried out.
3.For this project, the complete coordination with the company in the design and implementation aspects was done by me as a group leader.

2. DSP/VLSI implementation OFDM transceiver.
OFDM scheme, which is accepted as the physical layer for 802.11a, 802.11g and HIPERLAN2 wireless standards, has a major attraction in the industry. The implementation of a complete OFDM system compatible with 802.11a standard for wireless LAN application has been attempted by a group of four members. Suitable architectures for various modules were chosen based on the compatibility with the aimed application and performance by me as a group leader. OFDM transceiver mainly constitutes:
1. 64 point IFFT/FFT.
2. QAM - 64 modulator/demodulator.
3. Channel estimation, Equalization in receiver.
4. Bit loading in transmitter.
4. Time and frequency synchronization units.
5. Reed Solomon Encoder/decoder.
6. A Convolutional Encoder and Viterbi Decoder for concatenated Scheme.
My role in this project:
1.The algorithm and architecture identification and MATLab simulation for many of the modules of the complete transceiver.
2.VLSI implementation of channel estimation and equalization units.

3) FPGA implementation of Turbo Coder/Encoder:

The Turbo coding is an advanced Forward Error Correction scheme, which is a standard component in Third generation 3G wireless communication systems. This is a module in the communication system designed for the MICRO SATELLITE project, which is a joint venture of ISRO and Anna University.

Turbo codec Specification:

i) Fully complies with 3GPP specification (3GTS 25.12.212 Ver3.3.0)
ii) No. Of states=8.
iii) Rate of encoder =1/3
iv) Performance of BER of 1/10*exp (6) for 1.5db SNR.
v) Block size=5114.
vi) Interleaver: 3GTS 25.212 ver 3.3.0 compatible.
vii) Decoder algorithm: MAP (BCJR)

My contribution in this project:
1.The complete study of 3G spec as for as Turbo codes is concerned.
2.Algorithm and architecture selection for both encoder and decoder implementation
3.VHDL simulation and testing of the decoder unit.
4.MATLab simulation of the complete encoder and decoder units.

4.VLSI implementation of Motion Estimation unit for MPEG_4 video coder.

Content based functionalities such as content based coding and retrieval, are the enhanced features of MPEG-4 standard over the previous MPEG and JPEG standards. In the undertaken project a motion estimation unit which occupies more than 50% of hardware area of a complete video encoder was implemented for two algorithms (MAE-FSA and MIN-MAX). It includes an efficient segmentation unit to support content-based functionality, so that the speed, performance and functionality requirements of the MPEG-4 standard are satisfied. A motion compensation unit was also implemented. This was an individual project and is the Master degree thesis.

5.VLSI implementation of DCT/IDCT and SADCT architectures.

Another computationally intensive part in video compression is DCT/IDCT, which occupies 40% of hardware area. The Chen's algorithm was chosen for implementation of DCT. Since the multipliers consume lot of silicon area, a multiplierless implementation was chosen. But, it was observed that the maximum operating frequency gets affected drastically due to this. Similarly for SADCT an area efficient architecture was chosen and was found to satisfy the speed requirements of MPEG-4.


Father's Name : N.Subramanian B.E.
Sex : Female
Date of Birth : 20th June1978.
Nationality : Indian
Passport details :
Passport No : B3079676
Date of Issue : 27.12.2000.
Year of Expiry : 2010
Reference : Dr.P.V. RAMAKRISHNA,
Assistant Professor,
Anna University, Chennai

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