In Reply to: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!! posted by Rupa on 08/20/02 at 2:18 AM:
RAJESHKUMAR BHUPENDRABHAI SINGWALA
Permanent address: -
5/1275, HARIPURA SOISHERI NO: - 2, SURAT-395003, GUJARAT-INDIA.
X PHONE: 0261-2450348.
X E-MAIL: - email@example.com
« To seek the suitable opportunity where by utilizing my skills and knowledge gained in the engineering & technological areas and can excel the generic technologies in the engineering field for the growth of the industry and reach the level of self-actualization.
« As a lecturer in Electronics dept. at Sarvajanik College of Engineering and Technology, Surat-Gujarat from February-2001 to February-2002
« As a design engineer at Chip core Pvt. Ltd, Surat ĄV Gujarat from 5th AUG-2002 to till date.
Industry: (Chip Core Pvt. Ltd)
« Various components of 8085 micro processor chip design using VHDL (Modelsim Mentor Graphics Tool)
« Encryption and Decryption Algo.(AES,DES)using VHDL (Modelsim Mentor Graphics Tool)C-DAC, New Delhi
« Various Components of PCI ĄVM32 Interface core in VHDL using Modelsim (Mentor Graphics) Tool.
« Monitoring and controlling the speed of printing machine shaft using 8051 controller chip
« Morse Decoder in VHDL using Modelsim (Mentor Graphics Tool).
« Data Queue in VHDL using Modelsim (Mentor Graphics Tool).
« March - 2002 to July ĄV 2002
Post Graduate Diploma in VLSI Design from C-DAC, ACTS, New Delhi. Course module consists of Advance Digital Design, VHDL, Verilog HDL, CMOS VLSI Design and System Architecture.
« 1996-2000 South Gujarat University, Surat, Gujarat
X Studied Mobile Communication as an elective subject (GSM, TDMA)
X Studied courses on Fibre Optics & Satellite Communication
X Very good knowledge of 8085 & 8086 programming
X Studied course on VLSI & DSP
« Diploma in VLSI from C-DAC : 77 %
« B.E : 71.00%
« HSCE : 69.57%
« SSCE : 72.00%
« EDA Tools: MODELSIM 5.5e Simulation Tool, Aldec - ACTIVE HDL 5.1 SimulationTool, Leonardo Spectrum V20001Synthesis Tool, IRSIM Simulation Tool, XILINX Design Manager 3.1, Magic Layout Editor, SMASH 4.1
« Languages: VHDL, Verilog HDL, C, C++, JAVA, VB6.0.
« Methodologies: HDL Simulation, Synthesis, FPGA
Mapping (Placing and Routing)
« Administrator: Windows-95/98/00, Window NT-4.0,
« Intelligent network services
« Time management skills
« Dynamic team player
« Sense of responsibility
« Excellent skills in communication
« Creative and resourceful
« Date of Birth : 19-02-1979
« Marital Status : Single
« Languages Known : English, Hindi, Gujarati
INTERSTS AND ACTIVITIES
« Time management, traveling, reading, sports, programming, participation in the various quizzes and puzzles etc.