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Date: 04/25/03 at 11:10 AM
Posted by: budi shrinivas murty
E-mail: b_shrinivas10@yahoo.co.in
Message Posted:

In Reply to: Re: VLSI DESIGNER posted by ABDUL RAUF on 01/20/03 at 2:11 AM:

Looking for a lively and stimulating environment to work, in which company would not only offer me deep and diversified exposure, but would also enhance skills as an aspiring student of Electronics and Communication and also enable me to participate actively in the business process and appreciate it totally.

Educational Qualification:
Pursuing six-month certificate course in VLSI Design (will be completed by Jan'2003) from Deptt.of Electronic Science, University of Pune, Pune.

Course module of VLSI:
Digital Design, C-MOS VLSI, Design Hierarchy, Architecture of CPLD & FPGA, Hardware Descriptive Language (VHDL and Verilog HDL), Synthesis of module coded.

VLSI Project
Title : 32 - bit PCI Match Maker (Master)
Guide : Mr. Sunil Puranik
Project Manager PMC Soerra
Device Used : FPGA,Xilinx.
EDA Tool : Xilinx Foundation series 4.1,Modelsim.
Lanaguage: VHDL
Description :
A 32 bit PCI Match Maker it is basically design to facililtate communication between any Add On device which is not PCI complient with PCI bus on the system.This Match maker takes care of all the PCI bus protocol on one side and communicates with the Add On using FIFO on the other side by isolating the Add On from the PCI bus protocol.Two FIFO of 32 X 8 is used ,one is communicate from PCI to Add ON and other is from Add On to PCI.Both side clock is taken common.PERR ERR and SYS ERR is not implemented.Four Add On devies can communicate.
According to state machine blocks are divided and coding is written, after that whole module is combined to get the final coding.

Gate Score : 73.31.

B.E (Eqv) (Electronics and Tele - Communication) with 58.05%(Theoretical) from A.M.I.E.T.E, New Delhi.

Diploma in Electronics and Tele – Communication with first class 61.5% from Amravati University, Maharastra.

Major Subjects:
Analog and Digital Design, Circuit Theory and Design, Micro Processor, EMF Theory, Signal System, Communication System, Basic Electronics, Control System, Instrumentation Engineering.

Optional Subjects:
Computer Network and Digital Hardware Design

·Significant Project:
Development of TSM (Time Switch Mux-Demux card), which is a sub functional part of MAX (Main Automatic Exchange) using VLSI Technique. The language used is Verilog Hardware Descriptive Language. This project has been made in ECIL (Electronic Corporation of India Limited, Government of India Enterprise).

·Project Details:
As a part of my project I have chosen development of Time Switch Mux – Demux (TSM) card which is a part of TSU (Time Switch Unit). The language used for designing TSM (Time Switch Mux Demux) card is Verilog HDL(Hardware Description Language). As the number of IC is more and is widely varied it occupies large space and leads to many production related problem. Using VLSI (Very Large Scale Integration) design techniques that problem could be eliminated. The one or two VLSI devices sufficient for total logic to the input output specification of TSM card. C-DOT (Center for Development for Telematics) has design MAX (Main Automatic Exchange) and transfer the technology to manufacturers like ECIL, BEL, BHEL etc.

The Mux-Demux card is the gateway to Time Switch module various function are classified as follows

1.Input interface
2.Mux logic
3.Demux logic
4.Conference logica
5.Output logic.
In this project the activities included study of specification and function, Identification of different blocks, Representation of block identified in Verilog HDL, Preparation of test benches for testing the logic, synthesis of logic described.

No. of Candidate: 1

Duration: 4

· Personal Profile:
Fathers Name: Shri B.N.Murty
Date of Birth: November 10th, 1977
Marital Status: Unmarried
Sex: Male

Computer Skills:
Certificate of Merit from SSI (Unix and C).
s Certificate course in Information Technology from CMC.

Address for Communication:

F-3 Civil Line ,Uttai Road.

Tel. : 07882 322140
e-mail: b_shrinivas10@yahoo.co.in

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