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Subject: Re: VLSI DESIGNER

Date: 01/20/03 at 2:11 AM
Posted by: ABDUL RAUF
E-mail: arauf1973@rediffmail.com
Message Posted:

In Reply to: VLSI DESIGNER posted by suhas s kulkarni on 10/07/02 at 4:40 AM:

B-8/4 Park Site colony, Phone No.0091 22 5182820
Vikhroli (west), or 00971504228688
Bombay 400079 India . Email: arauf1973@yahoo.co.in

Abdul Rauf Abdul Karim

Career objective: Building career in VLSI field utilizing my expert skills in the area.

Experience:
March-Aug 2002:Working as Co-ordinator for Value Added Services in Jumbo Electronics
L.L.C UAE.
 Working on High End Communication and IT product installation.
 Management and Technical support to the Installation team.
 Handling Team of three Technicians.
 Preparing Duty sheet on AS400 operating system.
 Handling Insurance Scheme.

Feb2001-August 2001: Undergone training at V3logic Pvt. Ltd. Bang lore, India.
 RTL coding using Verilog and VHDL,
 Writing test benches for simulation using Model Sim.
 Digital Design using Verilog.
 Advance Verilog Synthesis verification and static timing analysis.
 Design using PLDs-FPGAs and CPLDs.
 Finite state machine.
Simulation Tools:
ModelSim.SE.
Synthesis Tools:
Xilinx (foundation series),
Leonardo Spectrum.
FSM Analysis : Renoir
Projects:
Mini Project :-

1) Title : Universal Asynchronous Receiver And Transmitter .
Organization : V3 Logic (p) Ltd, Bangalore.
HDL : Verilog.
Team Size : 2
Role : Analysis, Design, Coding & Testing.
Responsibilities : Heading the module of this Project.
Designing and Developing and testing each module.
Description :
This project uses the basic concepts of VERILOG and
Finite State Machines for modeling of UART .The 16550 is a programmable communication interface designed to connect to virtually any type of serial interface. It has four parts namely Receiver Transmitter Control Logic and Modem. In this UART Asynchronous Serial Data stream is transmitted and received in serial fashion.

2) Title : Direct Memory Access Controller (8237).
Organization : V3 Logic (p) Ltd, Bangalore.
HDL : Verilog.
Team Size : 6
Role : Analysis, Design, Coding & Testing.
Responsibilities : Heading the module of this Project.
Designing and Developing and Testing each module.
Description :
This project uses the basic concepts of VERILOG
And Finite State Machines for modeling DMA. The 8237 is a 4(I/O) Channel DMA Controller Used to connect the I/O and Memory directly with out any interference of CPU.It has Blocks mainly,Data/AddressBlock which has 8 datelines Multiplexed with Address lines (AD0-AD7) and 16 Address lines Read-Write Control Logic ,Control Logic & Mode set Register . It operates in Slave Mode & Master Mode. Control Logic is implemented using FSM.

4) Title : 4 Bit Microprocessor.
Organization : V3 Logic (p) Ltd, Bangalore.
HDL : Verilog.
Team Size : 1
Role : Analysis, Design, Coding & Testing.
Responsibilities : Heading the module of this Project.
Designing and Developing and Testing each module.
Description :
This project has been done using the concepts of verilog.
In the 4 Bit Microprocessor 4 bit Data Bus & 4 Bit address Bus are used with out Multiplexing. This Processor is works good for 16 Instructions. The main Blocks are Alu, Instruction Decoder, Registers B,C,D,E,H,L & Temporary Registers W,Z .all registers including Program Counter & Stack Register are 4 bit length.

Main Project :-

Title : PCI Master V. 2.2
Organization : V3 Logic (p) Ltd, Bangalore.
HDL : Verilog.
Team Size : 6
Role : Analysis, Design, Coding & Testing.
Responsibilities : Heading the module of this Project.
Designing and Developing and Testing each module.

Description :

Specifications
-32 bit data transfer.
-33 MHz operating frequency.
-Memory space mapping.
-Error reporting by Target Abort Method Following
Schemes are to be implemented in the design.
-Target only device.
-Termination method supported is Target Abort.
-Commands supported are :- Memory read, Memory write,
Configuration read & Configuration write.

Design Baud Rate Generator, LFSR, and ALU etc.

Attended workshop's on a) "Elementary Sessions on Digital Signal Processing"
By- Prof. Ashok Rao,
Indian Institute of Science Bangalore.
b) "ASIC Design Issues"
By - Prof.Shrinivasan
Indian Institute of Technology Chennai.
c) “CMOS Technology”
By- Prif.K.N.Bhatt
Indian Institute of Technology Chennai.


June 1991 –April 1992: Service Engineer at Advance Telecom Pvt.Ltd.Bombay.
 Card Level Maintenance of copier, fax etc.


June 1992 - June 1995: Equipment Technician at Dynarabia Co. Ltd, Riyadh, Saudi Arabia
 Card Level Maintenance of copier, fax etc,
 Periodic Preventive Maintenance of all office equipment.
Dec 1990 - April 1991: (Academic Project) Design Multifunction Frequency Meter.

April 2000-Sept 2000:(Academic Projects) PC based RF Strength Meter.
 PC based RF meter is use to measure the strength of RF signal.
 It is use for establishing a new Radio or Paging station.

Education:
Oct 2000 : Bachelor of Engineering (Electronics and Communication Engineering), Gulbarga University, Gulbarga, India. Graduated in Oct 2000 with First Class Grade.62%.
Sept 1991: Diploma in Electronics Engineering, from Board of Technical Education, Bombay, India, Graduated in September 1991 with First Class Grade.
Post Graduation Diploma:
Feb 2001 –July 2001 : Diploma in VLSI design.V3 logic Pvt .Ltd.Banglore.
Software & Hardware Skills:
 HDL Languages: Verilog and VHDL,
 Operating systems: AS400,MS-DOS, Windows 98, Unix
 High Level languages: C, Basic, Fortran 77
 Assembly language: For Intel 8085/8086 Microprocessor
 Word Processors: Word 97/2000, WordStar 6.0
Spoken Languages: English, Hindi, Marathi, Urdu, Arabic.
Personnel Details :
Date of Birth : 11-04-73
Pass Port : K-221075

Present Address : Door No.30, I cross,
Gangappa Block, 5th Main,
Ganganagar, Banglore.32

Place: Abu Dhabi
Abdul Rauf Shaikh



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