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Date: 01/06/03 at 3:04 AM
Posted by: Ajaya Kumar
E-mail: ajaya1202n@yahoo.co.in

In Reply to: Looking for job in VLSI/ASIC design posted by Rishi Sehgal on 10/29/02 at 3:27 AM:

RESUME

AJAYA KUMAR
VLSI / III / 47, ER&DCI
ANUSANDHAN BHAWAN
C-56/1, SECTOR-62, NOIDA (U.P)
Pin-201307
Ph. (0120) 24584102, 24580523.
E-mail : ajaya1202n@yahoo.co.in

OBJECTIVE:
To work efficiently in the field of VLSI Design and work towards a good foundation and career in this industry.

QUALIFICATION:
B.E. (Electronics & Communication) with 80% marks from Agra University.

ADDITIONAL QUALIFICATION:
6-months full time training in VLSI Design from Electronic Research & Development Centre of India (Ministry of Communication & Information Technology Govt. of India) Noida (U.P.).

PROJECT WORK:
1: -Project Name : Parabolic Reflector with Receiver.
Duration : 15 Days.
Team Members : Five.
Brie : We had made parabolic reflector and receiver for catch the Sahara Channel.

2: -Project Name : Design & Development of SRAM.
Duration : 10 Days
Team Members : Two
Tools : Virtuoso (Layout Editor)
: Dracula (DRC)
: Spectra (Schematic Simulation Tool)
: SPICE (Simulation Tool)
Role : SPICE Modeling, Schematic Diagram
Brief : We had made schematic circuit (1024 *8 bit) and applied DRC. We
also create layout with the help of Virtuoso.
3: -Project Name : VHDL Coding of FIR Filter(DSP).
Duration : 10 days
Team Member : Two
Tools : LDV 3.2 (VHDL Coding)
Role : Write the VHDL code.

OTHER TRAINING:
1-month training on CCTV of Electronics Department in AAI (Airport Authority of India)
I.G.I. Airport New Delhi.

SKILL SET:
LANGUAGE:
HDL Language : Verilog.
: VHDL.
SPICE (Simulation)
Programming Language: C,C++.
EDA TOOLS:
:LDV 3.2 (NCVHDL, NCVERILOG SIMULATOR).
:Ambit Build Gates (Logic Synthesis).
:Virtuoso Layout Editor.
:Dracula (DRC).
:Spectra (Simulation Tool).
:Diva.
:Silicon Ensemble (P&R).
:Xilinix Spartan II Series (FPGA).

OTHER:
Embedded System.
PLATFORM:
Sun Solaris, UNIX.

SKILL
Accept the challenge in odd situations. Keen to work with target based Industry. Strong analytical and interpersonal skill. Hard worker and a team player. Best negotiation skill. Willing to fulfill the commitment.

PERSONAL DETAIL:
Father’s Name : Mr. Ram Prakash Gupta.
Date of Birth : 16th Nov. 1978.
Nationality : Indian.
Languages Known : Hindi, English.

DATE……………….
PLACE………………

(AJAYA KUMAR)

Follow Ups:

  Re: Looking for job in VLSI/ASIC design kamalakannan   Posted at: 06/06/03 (0)

  Re: Looking for job in VLSI/ASIC design Senthilvadivu   Posted at: 05/06/03 (4)

  Re: Looking for job in VLSI/ASIC design M.GOKULAKRISHNAN   Posted at: 08/17/03 (0)

  Re: Looking for job in VLSI/ASIC design kamalakannan   Posted at: 06/06/03 (0)

  Re: Looking for job in VLSI/ASIC design Ajaya kumar   Posted at: 05/06/03 (1)

  Re: Looking for job in VLSI/ASIC design kamalakannan   Posted at: 06/06/03 (0)

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