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Subject: Looking for job in VLSI/ASIC design

Date: 10/29/02 at 3:27 AM
Posted by: Rishi Sehgal
E-mail: rishi@ureach.com
Message Posted:

I have graduated with a Master's in Computer Engineering and i am staying in the bay area right now.I have work experience with IBM in the area of ASIC design.I am familiar with circuit dsign,Logic design,RTL coding,Synopsys and Cadence tools and IBM ASIC tools.
I am enclosing a brief copy of my resume with this message.
Please contact me incase you suitable oppurtunities.
Thank you.

Name : Rishi Sehgal
Address: 1000 Escalon Avenue,
Apt A-2002,
Phone : 408-390-2653.
Email : rishi_sehgal@yahoo.com

To obtain a position in the in the field of VLSI/ASIC design which best
utilizes my knowledge and experience.

1)B.Tech in Electronics and Communications Engineering,
Jawaharlal Nehru Technological University.
2)M.S in Computer Engineering,
University of Louisiana at Lafayette.

Computer skills:
Languages: C,C++,Tcl,Perl.
Operating Systems: DOS,Solaris,AIX,Windows 95,Windows NT.
Web tools: HTML
CAD Tools: Magic 6.5, Hspice, Avanti Waves, Cadence Design Framework,Cadence Virtuoso, LVS, DRC, Synopsys Design Compiler,Synopsys Power Compiler.
ASIC Design Tools: ASOK, TheGuide, IBM Booledozer,IBM Clockpro,IBM TestBench,IBM Einstimer.
HDL: Verilog,VHDL.

1)Worked with IBM as ASIC Front-end Design co-op (Jan'02-May'02). Job responsibilities included working with synthesis team, design for test synthesis functional and test clock synthesis, scan insertion, JTAG insertions,CMOS checks, static timing analysis and timing closure.
2)Worked as Intern (May’01-Aug’01) at the IBM ASIC Design Center with the ASIC Front-End design group. Job responsibilities included evaluating Design Compiler synthesis parameters in order to attain high DFT coverage of the chip, functional and test clock planning, scan insertion, performing static timing analysis and timing closure.
3)Worked as Design Engineer (Jan’00-May’00) at National Remote Sensing Agency(India) in the VLSI design group.Job responsibilities included FPGA modelling at the block and the system level.Tools used included Verilog, VHDL, Altera MAXPLUS, Synopsys Design Compiler and Perl.
4)Worked as Research Assistant (Aug’01-Dec’01) with the VLSI design group under Dr Magdy Bayoumi, Director of CACS, University of Louisiana, Lafayette.Tools used included Verilog-XL, Design Compiler, Cadence Virtuoso, Magic, Hspice and Avanti Waves.

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