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Subject: Re: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!!

Date: 10/21/02 at 2:03 AM
Posted by: Naveen Khapali
E-mail: naveenkhapali@hotmail.com
Message Posted:

In Reply to: Re: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!! posted by Naveen Khapali on 10/21/02 at 2:00 AM:

Sir/madum, i am looking for a entery level job in vlsi design field.


No.15, 11th Main,
RPC Layout, 2nd Stage,
Vijaynagar, Bangalore-40.
Tel: - +91-80-3388611.
Email: naveenkhapali@hotmail.com

Naveen S. Khapali

Personal objectives

I am seeking a challenging position with a company that is rapidly expanding and offers good advancement potential, where an individual is recognized by his work. I just got my Bachelors degree in Electronics and Communication Engineering at Basaweshwar Engineering College Bagalkot, under VTU Belgum. I would like to use my knowledge in VLSI design and see forward to handle new projects where I can demonstrate building high speed/high density, production worth design structures.


Work carried out by me in the VLSI field includes, Transistor Level Design Layout, Memory Designing, Layout Migration, Place and Route, Physical Verification, Timing Analysis and Parasitic Extraction.

I am also well conversant with process technology and have experience with custom macro blocks such as RAMs, Physical Verification, Layout Migration including DRC, etc.

I was a member of the Dumpoyee Fanout Team that installed IC Design Software and assisted the faculty of B.V.B.C.E.T, Hubli in training on the above mentioned VLSI issues and completing the mini project, on behalf of Karnataka Microelectronics Pvt. Ltd., from 15 July to 15 September 2002.


Qualification : BE in Electronics and Communication Engineering

School/College : Basaveshwar Engineering College, Bagalkot.

Month/Year % Obtained
of Passing

May 1999 1st SEM 72.3%
Dec 1999 2nd SEM 71.7%
July 2000 3rd SEM 70.8%
Oct 2000 4th SEM 71.3%
May 2001 5th SEM 72.5%
Oct 2001 6th SEM 78.6%
Apr 2002 7th SEM 76.2%
Sep 2002 8th SEM 93.1%

P.U.C : JSS College Dharwad June 1998 72.0%

SSLC : Poorna Prajnya English Apr 1996 71.0%
Medium High School,
Rampur, Rabkavi.

BE Aggregate: - 77.68%

Memberships: - IEEE Student Member since 1999.


1. A project on CMOS high speed low power SIX BIT GRAY CODE COUNTER CHIP using 1.6-micron technology during my third year of BE in attachment with Karnataka Microelectronics (KarMic) Manipal.

2. IDCT forms an inevitable part of image compression. The project work carried out at KarMic Manipal for final semester gives the VLSI CMOS Implementation of 2-dimensional IDCT Architecture. In this project, the architecture of 2D-IDCT using optimal number of multipliers and adders has been derived. The project discusses the design and implementation of IDCT CMOS integrated circuit. The core operates on the 8 x 8 input block of DCT. The input and output precision is 15-bit to and from the IDCT. The layout has been generated with a 0.35m CMOS using Ocean and Magic tools and measures under 98 mm2."The aim of this project was to develop an IDCT core for image compression applications that utilizes less area with low power consumption, at faster speed.”

Computer Skills

Proficient in working with,
1.Operating System Windows 95/98/2000. LINUX 7*
2. Languages -- C
3. Assembly Languages -- 8085.
4. Hardware Description Languages -- VHDL, SPICE.

I am also proficient in using packages such as
1. MAGIC (CMOS full custom layout Editor on LINUX platform).
2. OCEAN (CMOS semi-custom layout Editor on LINUX platform).
3. SPICE (Simulation Program for Integrated Circuits Emphasis)

Achievements and Accomplishments

1. I was the Chairman of IEEE Student Branch at BEC Bagalkot for the academic year 2001 and Secretary of the same for the year 2000.
2. Selected to undergo one-day camp on Leadership Training for Students, organized by IEEE Bangalore Section at IISc Bang.


1. Received award for securing top in Microwave Circuits and Devices in V sem.
2. Second place award for presenting papers on VLSI BASICS FOR CMOS DESIGNS and NETWORKING USING TV CABLES.
3. Bagged the Best Student Award for the year 1996 in SSLC.

Papers Presented,

1. VLSI BASICS FOR CMOS DESIGNS, under ACME, BEC Bagalkot in VI sem.
2. VLSI DESIGN-CMOS SIX BIT GRAY CODE COUNTER at TECHNISIUM, a National Level Paper Presentation Contest at SIT Tumkur in VI sem.

Extra Curricular Activities

1. Organized activities such as SECTIONAL TECHNICAL COLLOQUIUM (zonal level), TECHNICAL QUIZ CONTEST, and PUZZLE CONTEST (college level) while bearing the position of CHIR of IEEE Student Branch BEC Bagalkot.
2. One event SOFTEST-2000 (State Level) while Secretary of IEEE Student Branch BEC Bagalkot.
3. Participated in Table Tennis tournament, zonal as well as college level.
4. And has hosted some of the programs while undergoing my BE education

Subjects of interest

1. VLSI Design.
2. VHDL, Computer Organization and Architecture.
3. Microprocessor 8085, Digital Electronics

Personal profile

1. Father's name: Shri Siddappa M. Khapali.
2. Date of Birth: 1-07-1980.
3. Hobbies: Listening soft music, enjoy playing Table Tennis and volleyball.

About Myself: I am versatile, fluent in English language, loves work. Good in administrating/managing activities. Adept in picking up responsibilities, new skills and likes to keep busy and relishes new challenges.


1. Dr S. S. Mahant-Shetti
Karnataka Microelectronics Pvt. Ltd.
“INDIRA”, #31, 14th Cross,
ALN Layout, Manipal-576119
Ph.No: (0825)571745.
Email: mahant@ieee.org

2. Shri S G. Kambalimath
Dept. of Electronics and Communication Engineering
Basaveshwar Engineering College, Bagalkot.
Ph. No: (0835) 436305
Email: sgkambalimath@rediffmail.com

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