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Subject: Re: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!!

Date: 10/18/02 at 2:06 AM
Posted by: shankar
E-mail: shankar_jag@yahoo.com
Message Posted:

In Reply to: Excellent Opening for RFIC /ASIC/VLSI/CMOS professionals!!!!!! posted by Rupa on 08/20/02 at 2:18 AM:

RESUME


SHANKAR Y.J E-mail: shankar_jag@yahoo.com
Ph.(91) 80-3397991 Bangalore

SUMMARY :
Having 2 years of experience in Technical Support for Avanti's Place & Route tools Apollo & Astro. Thorough knowledge in Physical Design , Degital, CMOS concepts, Layout Design, scheme language,LEF/DEF, Antenna Issue's & stick diagrams. Excellent team player with good communication skills.

OBJECTIVE:
Contribute to the Corporation's growth through an efficient systems environment by utilizing existing skills and knowledge and to be a good ASIC Designer.

EXPERIENCE DETAILS:
Worked as Support Centre Engineer in Synopsys(Avant!) India Hyderabad from August 2000 To June 2002.

EDUCATIONAL PROFILE:
Completed B.E. (ELECTRONICS & COMMUNICATION) secured 68% From Basaveshwar Engineering College Bagalkot, affiliated to Karnataka University Dharwad in 1999-2000.

Completed Xth (AISSE) with 77% and XIIth (AISSCE) with 74% from Jawahar Navodaya Vidyalaya Narayanpur Bidar.

TECHNICAL SKILLS

EXPERTISE In Avant! Tools : Milkyway, Apollo, Astro
Saturn, Mars-Rail/XTalk
Astro-Rail/Xtalk.
EXPOSURE to Avant! Tools : Enterprise, Star RC/XT,
JupiterP/XT, Hercules.

AREA OF SPECIALISATION : FloorPlanning, CTS,
Timing Analysis, LEF/DEF,
Antenna & Rail Analysis.

SOFTWARE SKILLS : C C++ Perl TCL/TK
Scheme programming.
Operating System Known : Unix

PLATFORM WORKED on : HP-UX, Sun Solaris.


SELECTED ASSIGNEMENTS

Project#1

Project name : JAVA PROCESSOR
Duration : 4 Months
Team size : 5
Responsibilities : DataPrep FloorPlan Place & Route
Timing Optimization of a block.
Client : Time To Market, USA.
Tools Used : Milkyway, Planet-PL, Apollo, Saturn.

Abstract :
Hierarchical design with five soft macros using Technology of 0.25 micron. Having powerstraps & rectangular rings of width 100 microns each. And inside of each softmacro powerstraps placed at every 500 micron.

Goal Achived :

1. Hierarchial Floorplanning of Top Cell with core utilization of 75%, along with floorplanning of each soft macros with utilization of 80%. (Tool used Planet PL & ApolloII)

2. Timing Driven Placement for one soft macro with constraints from Synopsys Design Constraints(SDC). (Tool used ApolloII & Saturn)

3. Clock Tree Synthesis (CTS) of each soft macro with a target skew of 0.2ns and phase delay 0f 2ns.The CTS is carried out for the Top Cell also.(Tool used ApolloII).

4. Routing of each macro and the Top Cell. (Tool used ApolloII).

5. Physical Verification (DRC & LVS) for each macro and the Top Cell. (Tool used Hercules).


Project #2:

Project name : Standard Cell Library Development
Duration : 2 Months
Team size : 1
Responsibilities : Develop the STD cells with
DRC & LVS clean.
Tools Used : Milkyway, Enterprise & Hercules
Brief Explanation : Designing of Standard Cells of 0.25 technology using the given spice netlist with DRC & LVS clean.


Test Cases 1:

Project name : DieSize Reduction
Duration : 2 Months
Team size : 1
Responsibilities: To achieve the core Util 98.5%
Tools Used : Milkyway,Apollo.
Brief Explanation: Reduce Die size with a core
utilization of 80% to 98.5%, using different techniques.
It Contains 19 hard macros and 28k standard cells.

Test Case 2:
Project name : Timing Driven Placement
Duration : 2 Months
Team size : 1
Responsibilities: To achieve +ve slack .
Tools Used : Milkyway,Apollo, Saturn
Brief Explanation: Flat design with an
initial slack of -61.3ns, Achieved the +ve slack
by using differnet techniques.

Benchmark: (Using both Apollo & Astro tool)

1. Bench Mark For NEC involving diesize
with 30k std cells with core utilization of 96%.

2. Bench Mark for NEC involving
High Fanout Nets, high load capacitance and
Transition violations, Timing Constraints from SDC file.

3. Bench Mark for NEC involving Power and XTalk Analysis
for a design having 50k STD cells.


Project Work : Developed as part of the curriculm
of Engineering.
Project name : A DSP BASED SPEECH CODING SYSTEM
USING VECTOR QUANTIZATION TECHNIQUES
To reduce the channel bandwidth,by a bit rate reduction factor of 4 using the LBG(LioydBuzoGray) and K-Means algorithms, &
VQ tech's. For Data Security RSA Algorithm used.
Implemeted using DSP Processor kit TMS320C25 .

Personal Details:
----------------
Name : Shankar Y Jagannathi

Date of Birth : 06/06/1976

Marital status : single

Passport Details: 1. Passport No. A8721507
2. Place of Issue: Bangalore .
3. Date of Issue : 27/03/2000
4. Date of Exp. : 26/03/2010

I here by acknowledge that the
above information is true to the best of my Knowledge.


Yours Faithfully
(SHANKAR)



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