In Reply to: Hardware VLSI/ Memory Design/ ASIC Engineer in BAY AREA Full Time/ Contract position posted by Chintan Purohit on 09/26/02 at 6:21 PM:
Name : Mr. Hemant R. Dandekar
Presently working with Krishna Institute of Engg & Technology
Ghaziabad as Lecturer in Electronics and Communication Deptt.
Currently Guiding the following projects:
1. Design of floating Point ALU and Implementation using VHDL.
2. Networking using Optical fibre.
Work Experience :
(July 2001 to Dec 2001)
Worked as a VLSI Trainee Engineer in ICIT Pvt. Ltd. Pune.
( Sept 1999 to Nov. 2000 )
Worked as a Design Engg. in Badave Engg. Pvt. Ltd. Pune
Job Profile :
*Design digital circuitry as per requirement and test it.
*Testing of an I/O cards using Microcontroller 8051.
*Writing a program for testing of a card in assembly language.
*Testing of a project at functional and environmental level.
*Testing of a project for EMI and EMC and Vibration level.
Paper Presentation : Paper Presented on "DSP Vs Conventional
Microprocessors", at AMITY School of Engg. & Technology, Delhi on
19th April 2002.
Projects Undertaken :
1.PCI based Data Acquisition System :
Sponsored by: IUCAA , Pune Duration : 03 months
Description : PCI local bus is a high performance bus for
interconnecting chips, expansion board , and processor /memory
subsystem. It is a synchronous bus architecture with all data
transfers being performed
relative to a system clock. The initial PCI specification
permitted a maximum clock rate of 33 MHz . Later , Revision of the
PCI specification extended the bus definition to support operation
at 66 MHz. At 33 MHz ,a 32- bit slot supports a maximum data
transfer rate of 132 Mbytes/ sec, and a 64-bit slot support 264
Project involves design of interfacing of local bus to PCI bus
using PCI-9050-1. The data recieve on local bus in two modes. In
mode zero, Serial data coming on Fiber optics converted into 32
bit data and transmitted on PCI bus. In mode one, first store this
incoming data in one RAM. When this RAM full then generates
interrupt for the PC to read data from RAM and for storage of
incoming data switch over to the another RAM. At the same time we
have check interrupt generated by PC for data transmission for the
Coding for receive and transmit data from the serial optic fiber
to the PCI bus and vice versa written using VHDL Language.
2.Two Axis Control System : ( M.E. Project )
Sponsored by:Badave Engg. Pvt. Ltd. Pune. Duration : 06
Description: The project involved simulation and study of
mathematical modeling of two-axis control system and its
implementation. Project consists of Controller , Amplifier ,
Motor, Encoder. The working of
amplifier to amplify the signal generated by controller and given
to the motor. The working of encoder to sense the actual position
and feedback to the controller. It also uses for the homing
purpose. ADSP 21060 DSP
processor was used as a controller.
The mathematical modeling and simulation of the system had done by
using MATLAB Software. The actual software was written into C
language for the DSP processor.
3.Microprocessor based Power Factor Control of Inductive load : (
B.E. Project )
Description: The project based on 8085 microprocessor and included
detailed assembly language programming and hardware. Project is
used to control the power factor of the inductive load. When the
inductive load is connected as
a load, the current lags behind the voltage by some angle. When
the inductive load varies the angle between voltage and current
also varies. The power factor depends on the angle between voltage
and current . For keeping the same angle even
thought the inductive load varies, the capacitor bank is used to
provide leading power factor and which will compensate it. The CT
and PT are used to sense the current and the voltages across load.
senses the voltage and current across the load and calculates the
actual angle and compare with the required angle accordingly
Capacitor banks comes into picture. The programming was done in
assembly language for 8085 microprocessor .
Software and Tools
*VHDL and Verilog HDL .
*Xilinx Foundation Series FPGA/PLD design tool
*Modelsim simulator and waveform viewer for VHDL
*Aldec simulator and waveform viewer for VHDL/Verilog
*Orcad simulator for VHDL.
*Knowledge of Basic electronic circuits and designing.
*Capable of debugging the digital PCB circuits.
*Knowledge of logic design in the field of computer
Address for Communication : House no 368, Chiranjiv Vihar,
Behind Shashtri Nagar,
Tele : 09810465439
Permanant Address : S/o R. V. Dandekar
Gandhi Nagar , Ward No. 3, Near Niranjan
Wardha. 442001 (M.S.) India
Tele : 07152-41443
E-mail : email@example.com
Passport No. :B 3358487
Date of Birth : 20 / 09/ 1976
Sex : Male
Marital Status : Unmarried
Languages Known : Marathi , English and Hindi .
Academic Details :
Exam Board/Univ Institute Passing Marks
Certificate Department June 2001 71%
coursein VLSI Pune of Electronics
Design and Science
System) Pune Govt. College June 2000 68%
of Engg.Pune 5.
(Power Nagpur B. D. College
Electronics) Engg.Sewagram June 1998 75%
VLSI Design Course Contents :
*CMOS process and Device Technology .
*Design principles of Custom , semi -custom , Datapath circuits
*Fundamentals of Programmable Logic
*VHDL , Verilog coding
*Study of FPGA and CPLD architecture like Xilinx 9500 CPLD and
*State machine and Schematic based designs
*Processor architecture and Processor design
Computer : C language, Matlab Control System Toolbox.
Languages Assembly Language of 8085/86 and
Computer: Platform- DOS , Windows 95 and 98
Knowledge Tools- MS-Office tools viz.MS Word.
Place : Ghaziabad Mr. Hemant R. Dandekar