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Subject: Re: US-Midwest: Digital/DSP Engineer(ASIC/FPGA/VHDL/VERILOG)

Date: 08/22/02 at 4:57 AM
Posted by: BALIREDDY RAVEENDRA
E-mail: brreddy01@rediffmail.com
Message Posted:

In Reply to: Re: US-Midwest: Digital/DSP Engineer(ASIC/FPGA/VHDL/VERILOG) posted by ATUL WAHI on 06/27/02 at 10:26 AM:

BALIREDDY RAVEENDRA

ADDRESS : H.NO : 16 - 1 - 483/17,
Saidabad colony,
Hyderabad.
EMAIL : brreddy01@rediffmail.com
brreddy01@yahoo.com
Phone +91-040-4079330

Career goal : To handle challenging projects in VLSI design and to extend my services for the development of organization .

Languages & Tools summary :
Languages : VHDL, Verilog, C, 8085 / 8086
Operating systems : UNIX , WINDOWS 95/98, NT
Similation Tools : Modelsim, Active HDL, ALTERA MAXPLUS II
Synthesis Tools : Leonardo spectrum, FPGA Express
Layout Tools : Magic, Irsim, Pspice
Placement Tool : Quartus (Altera Maxplus ii )


Academic qualification :

S.No Course Year of Pass Name of College % of marks
1 B.E ECE) 2001 osmania university 69 %
2 D.E.C.E(Diploma) 1996 S.V.Govt.Polytechnic 70 %
3 S.S.C 1993 Z.P.P.H School 71 %

Technical Experience :

Course : Diploma in VLSI Design .
Institute : Center for Diploma in Advanced Computing (C-DAC ), PUNE, India
Major : Advanced Digital Design, Designing with HDL's (VHDL / Verilog), CMOS layout design, System Architecture, FPGA & ASIC DESIGN, Synthesis concepts, Placement & Routing .
Project : Ethernet MAC (Medium Access Control) Receiver
Period : March 2001 - August 2001


Industrial Experience:
I am working as Graduate Engineer Apprentice ( GEA ) in R&D of Electronics Corporation of India Limited (ECIL) on VLSI projects from February 2002 to till today. Here my work is writing the VHDL coding for the test bench (only part of) of currently doing project and Verification of the project by using this testbench. In ECIL , i did the following .

1. Title Name : Analog to digital converter ( ADC)
Simulation : Active _ HDL
Synthesis : Leonardo spetrum
Description : It is one of the testbench module for the currently doing Sound Ranging System (SRS) project . In this ADC module a file operation is used for generating analog waveform, this input file is external to the this module . The ADC block mainly contain a FIFO, is used to read these values and store in it and send to the FPGA (the device for testing) under appropriate conditions.
Placement & Routing : Quartus ( Altera MaxplusII)

2. Title Name : Digital signal processing ( TMS320C32 )


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