In Reply to: Re: US-Midwest: Digital/DSP Engineer(ASIC/FPGA/VHDL/VERILOG) posted by ATUL WAHI on 06/27/02 at 10:26 AM:
ADDRESS : H.NO : 16 - 1 - 483/17,
EMAIL : email@example.com
Career goal : To handle challenging projects in VLSI design and to extend my services for the
development of organization .
Languages & Tools summary :
Languages : VHDL, Verilog, C, 8085 / 8086
Operating systems : UNIX , WINDOWS 95/98, NT
Similation Tools : Modelsim, Active HDL, ALTERA MAXPLUS II
Synthesis Tools : Leonardo spectrum, FPGA Express
Layout Tools : Magic, Irsim, Pspice
Placement Tool : Quartus (Altera Maxplus ii )
Academic qualification :
S.No Course Year of Pass Name of College % of marks
123 B.E (ECE)D.E.C.E(Diploma)S.S.C 200119961993 MVSR Engg.collegeO.U, Hyderabad .S.V.Govt.PolytechnicTirupati.Z.P.P.H School 69 %70%71%
Technical Experience :
Course : Diploma in VLSI Design .
Institute : Center for Diploma in Advanced Computing (C-DAC ), PUNE, India
Major : Advanced Digital Design, Designing with HDL's (VHDL / Verilog), CMOS layout design,
System Architecture, FPGA & ASIC DESIGN, Synthesis concepts, Placement & Routing .
Project : Ethernet MAC (Medium Access Control) Receiver
Period : March 2001 - August 2001
I am working as Graduate Engineer Apprentice ( GEA ) in R&D of Electronics
Corporation of India Limited (ECIL) on VLSI projects from February 2002 to till today. Here my work is
Writing the VHDL coding for the test bench (only part of) of currently doing project and Verification of the project by using this testbench. In ECIL , i did the following .
1. Title Name : Analog to digital converter ( ADC)
Simulation : Active _ HDL
Synthesis : Leonardo spetrum
Description : It is one of the testbench module for the currently doing Sound Ranging System
(SRS) project . In this ADC module a file operation is used for generating analog
waveform, this input file is external to the this module . The ADC block mainly
contain a FIFO, is used to read these values and store in it and send to the FPGA
(the device for testing) under appropriate conditions.
Placement & Routing : Quartus ( Altera MaxplusII)
2. Title Name : Digital signal processing ( TMS320C32 )
Description : This is main module used in testbench of our currently doing Sound Ranging
System (SRS) project . This is currently i am doing , the mail purpose of this is,
used for doing computations like floating point operations on the received data
from external memory and send the computed data to FPGA ( the device for
Projects Handled / Executed in C - DAC :
At C -DAC VLSI training various projects have done like,
1. 8 bit microprocessor
2. Bus arbitration logic
3. Ethernet MAC receiver
B.E Project : Test Pattern Generator for Indian Remote Sensing (IRS) Satellites using VHDL
Project brief :
The Test Pattern Generator is used to Simulate the data of various sensors of Indian Remote
Sensing Satellites. The Test Pattern Generator consists generating the data (contains Frame Sync code, Auxiliary information and video data) according to the data formats of various sensors of Indian Remote Sensing Satellites(IRS). The description of this Test Pattern Generator is developed by using ALTERA MAXPLUS-II simulation tool in National Remote Sensing Agency (NRSA) -HYDERABAD.
C DAC project : Ethernet MAC Receiver
Project brief :
The Ethernet MAC Receiver receives the data from the medium independent interface (MII) and checks CRC for received data (nibble of) and send to the next layer by checking various errors like length of each packet , CRC error etc .
1. Watching movies, cricket
2. Playing ball badminton, chess, shuttle.
3. Surfing internet, singing songs
Fathers Name : B.Obula Reddy
Martial status : single
Date of Birth : 07 /07/1977
Languages known : English, Telugu, Hindi
Address : H.NO : 16 - 1 483/17
Hyderabad - 500 059
EMAIL : brreddy01 @ rediffmail.Com
brreddy01 @ yahoo.Com
· Ability to work autonomously as well as in a team
· Good communication skills , Analytical & logical skills
· Self motivated and ability to motivate others
· Adaptability , flexibility, Hardworking and Open minded