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Subject: Re: recruitment operations in Electronics - MicroElectronics - Telecommunications

Date: 08/04/02 at 1:07 PM
Posted by: shinde rajesh k
E-mail: shinderk@rediffmail.com
Message Posted:

In Reply to: Re: recruitment operations in Electronics - MicroElectronics - Telecommunications posted by ATUL WAHI on 06/27/02 at 10:37 AM:

13, Jagdish Niwas,
Rd No-16,Kisan Nagar-3,
Wagle Estate,
Thane(West)- 400604
Maharashtra.
India.
Tel : 91-22-5811703

RAJESH KESHAV SHINDE shinderk@rediffmail.com

FATHER・S NAME KESHAV SONU SHINDE
DATE OF BIRTH 23 AUGUST 1979.
PHYSICAL FITNESS I do not wear glasses, am 5・8; tall and able bodied.
SEX MALE.
MARITAL STATUS SINGLE.
NATIONALITY INDIAN.
LANGUAGES KNOWN MARATHI, ENGLISH & HINDI
PASSPORT NO. B-3274946 (Valid).
WORK EXPERIENCE Jr. Design Engineer (45 Days)
Hind Rectifier Ltd.,
Bhandup, Mumbai. 78.

EDUCATIONAL DETAILS
DIPLOMA IN INDUSTRIAL ELECTRONICS: (Annual pattern / Summer 1998)
THROUGHOUT FIRST CLASS
V.P.M・s Polytechnic, Thane. (Board of Technical Educations, Mumbai).
Industrial Electronics
Project :- :TELEPHONE CONTROLLED SWITCH;
Able to control seven mains load via telephone line.
Using 8031 microcontoller (Assembly language)
Guide:- D. K. NAIK ( H.O.D.) V.P.M.・s polytechnic, Thane.

BACHELOR OF ELECTRONICS ENGINEERING : (June, 2001)
Lokmanya Tilak College of Engineering, Navi Mumbai. (University of Mumbai.).
Elective subjects
1. Data Communication 2. Microcomputer System Design.
Project :- :64Kbps MODEM;
Modem transmits data / information and change (modulate) the format depending the process, using a phone line to transmit data to another modem.
Feature :- 1. Line inteface :- 2-wire full duplex PSTN and Leased line
2. supports to both Synchronous and asynchronuse trnsmission
3. Automatic speed negotiation.
4. Data speed :- 300 bps V 64 Kbps.
5. Diagnostics :- Local Loop Back , Remote Loop back, BER tester.

Guide :- M. SATYANARAYANA.
Bharat Sanchar Nigam Ltd., Telecom Factory,
D.O.T., Govt. Of India, Mumbai-88.


POST GRADUATE DIPLOMA IN VLSI DESIGN: (Feb V 2002)
FIRST CLASS
CDAC, ACTS,Pune Terna EDA center ( Navi Mumbai)
Contents of course:
h Advance Digital Design.
h HDL simulation & System ( VHDL & Verilog )
h CMOS
h System architecture
h CPLD / FPGA
h Project
Project : : BLUETOOTH DATA ENCRYPTION ENGINE;
Project aim : Authentication and Encryption in bluetooth to make data transmission secure
Algorithms implemented
1. E0 V Encryption
2. E1 V To generate SRES and ACO
3. E2 V To generate different keys
4. E3 - for payload generation
Simulator :- Modelsim, Xilinx, Leonardo Spectrum.
Guide : V.M. WADHAI
CDAC convener, Terna EDA Center, Navi Mumbai.

SOFTWARE KNOWLEDGE
Windows-98 & DOS (operating system)
MS office, Smart work, Orcad, C, Assembly language programming, VHDL, Verilog.

EDA Tools (for Front end ):
ModelSim, Leonardo Spectrum, FPGA Express-Synopsys, Xilinx & Altera Tools, MAGIC.


SEMINAR ATTENDED IEEE (silver jubilee function ).
Venue : De ROYAL MADRIAN , Mumbai.

AREAS OF INTEREST Digital Logic Design, Digital communication
Microprocessor based Design, etc.

ACHIEVEMENTS Received scholarship from J. R. D. TATA for academic year 1999-2000
Won Medal at National Jambhori (Palghat, Kerala).

HOBBIES Internet surfing, Video-shooting, Photography, Cricket, Drawing, etc.

REFERENCE V. M. WADHAI (M. E.) Power electronics
CDAC convener,
Terna EDA Center, Navi Mumbai.


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