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Subject: Resume: 2 years Exp in VLSI Front End and Analog Design

Date: 06/09/02 at 11:53 AM
Posted by: Sayandeep Nag
E-mail: sayandeep_nag@yahoo.co.uk
Message Posted:

Date: 9th June 2002


The Human Resource Manager,


Subject : Regarding a suitable Position in your Organisation


Respected Sir/Madam,


As a Bachelor of Engineering in Electronics and Communication and approximately 2 years of relevant experience in the field of VLSI for both Full-custom and Semi-custom design implementation. My resume is enclosed for your kind perusal and a suitable position in you organisation.

I have a good amount of experience in processor architecture design and have also proficient in semiconductor device modeling for the purpose of simulation using PSpice. I have a good knowledge of both Xilinx and Altera FPGA / CPLD architectures and ASIC design methodologies. Presently i am working on MP3 codec core development .

Resume

Email: sayandeep_nag@yahoo.co.uk

Sayandeep Nag

#90, 6th Cross Inspectorate of Electronics Layout

Cholayanayakanahalli, R.T.Nagar P.O

Bangalore 560032

Ph. 91-80-3633343


Experience Summary


VLSI Design Engineer with approximately 2 years of experience in the design of Integrated Circuits with various stages of development including analyses, design, development, testing and documentation.


Skills

Strong Digital Design skills
State Machine Design
Verilog HDL Simulation and Synthesis
ASIC Design Methodology
FPGA / CPLD
CMOS and Active Elements Modeling Using HSPICE/PSPICE
Micro-controller based board level design
Real Time Operating System
Assembly Level Programming
Strengths

Experience in all phases of development life cycle, which includes analyses, design, development, testing, documentation and implementation.


Project Management skills, from requirement document generation to various phases of the DLC. Experience in proposal generation and resource estimation.


Competitive analytical skills. Strong team building and leadership skills.


Effective documentation and presentation skills.


High awareness of both CMM and ISO 9001 standards.


Educational Qualification


Bachelor of Engineering in Electronics and Communication Engineering

University: Bangalore University

College: Siddaganga Institute of Technology

Languages: Verilog HDL, C, and C++


Tools:

Front End Simulation : Xilinx ISE 4.1, Altera MaxPlus II, Quartus II, Modelsim

Silos III, Polaris (Avant!)


Synthesis : Explore RTL (Avant!), Synopsis FPGA Express, LeonardoSpectrum


Analog : Star HSPICE (Avant!), Microsim, PSPICE


DSP : Matlab.


RTOS : QNX, Keil.


Operating Systems: Solaris, HPUnix, and Windows 9x



Professional Experience


Present From April 2001 working with Benns Technologies, Bangalore as Member VLSI / ASIC Design Team : Joined Benns Technologies as a Member VLSI / ASIC Design Team. Helped Create ISO-9001 certified process for acquisition and distribution of Source and Documents related to projects for efficient release and Build Management both within the organisation and external.

Presently involved in the design and development of MP3 codec, which is being developed as an IP jointly in collaboration with Department of Applied mathematics. Indian Institute of Technology, Madras.

Involved in creation for the Architecture that we are proposing for the Indian Air Force Tele-medicine Pilot Project. The same has to be executed with six geographical locations within India, while the Hub will be at Medical Directorate New Delhi. Benns Technologies and Surya Soft Tech Ltd., Bangalore are jointly working on this project.

Involved in giving image compression solutions using standard H.263 for the purpose of video streaming and Teleconferencing.

Helped in designing Portable Radar Test System using MIL-STD-1553B for Aeronautical Development Agency, Bangalore.


From October 2000 March 2001 as a Trainee Design Engineer, in Future Techno designs Pvt Ltd, Hyderabad.

Worked as a team member in the Analog Design Team and Specialised in semiconductor device modeling for the purpose of simulation using SPICE.

Part of team involved in the development of MCS 51 architecture to be implemented on a 100 K gate FPGA.


From August 1999 March 2000 as a Trainee Engineer, in Aerospace Systems Pvt. Ltd., Bangalore.

As a Trainee in the Board Level design Team was involved in development of an Enlarged Main Display to be driven by Intel 87c51, as part of B.E. Final Year Project


Projects for Benns Technologies

Name of Project : MP3 Codec

Team Size : 5

Role : Concept Study, Requirement Analyses, Development of Specification, Design, Coding.


Details : Digital compression of audio data is important due to the bandwidth and storage limitations inherent in networks and computers. Algorithms based on perceptual coding are effective and have become feasible with faster computers. The ISO standard 11172-3 MPEG-1 layer III is a perceptual codec that is presently very common for compression of CD quality music. An MP3 decoder has a complex structure and is computationally demanding.


We have analysed several algorithms suitable for implementing an MP3 decoder, their advantages and disadvantages with respect to speed, memory demands and implementation complexity. We have also designed and implemented a portable reference MP3 decoder in Matlab.

Name of Project : Power MOSFET Modeling

Team Size : 1

Role : Study, Specification Analyses, Coding, Testing and Documentation.

Client : IXYS Corporation, USA.

Details : Understanding the Mosfet behavior from the data sheets and then developing the parameters in {Spice for simulation of the device

Name of Project : PCI Bus

Team Size : 7

Role : Study, Specification Analyses, Coding, Testing and Documentation.


Details : The PCI IP core (PCI bridge) is a bus bridge device between the WISHBONE SoC bus and the PCI local bus. Both sides of bridge can operate at totally independent clock frequencies. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus. Performance features include 32-bit bus interfaces on both sides, high level of performance and flexibility like burst data transfers, memory access optimizing command usage etc. The code is completely GENERIC ,which makes the core easily retargetable for any FPGA or ASIC technology.


Projects for Future Techno Designs Pvt. Ltd.

Name of Project : MCS 51

Team Size : 30

Role : Study, Specification Analyses, Coding, Testing and Documentation.


Details : Development of the Serial Port of Intel 8051 micro-controller of MCS 51 family using State Machine (FSM) for Transmission and Reception of Serial Data with a variable Baud Rate and four different modes of operation for both normal as well as multiprocessor environment and to write a RTL code for the above design using Verilog HDL.

Name of Project : FDC 8277

Team Size : 4

Role : Study, Specification Analyses, Coding, Testing and Documentation.


Details : Design and Development of Floppy Disc Controller Intel 8277 for Buffering and converting Parallel Data from CPU to Serial Data and Encoding using FM/MFM as specified by user and also decoding the Serial Data from the Disk, buffering and converting it into Parallel data for the use of the CPU and write a RTL code for the above design using Verilog HDL.


3. Name of Project : DMA Controller

Team Size : 4

Role : Study, Specification Analyses, Coding, Testing and Documentation.

Details : A single state machine consisting of eight states covering all the operations of the DMA

Projects for Aerospace Systems Pvt. Ltd.

Name of Project : Development of Enlarged Main Display
Team Size : 3

Role : Study, Specification Analyses, Coding, Testing and Documentation.


Details : Development of Enlarged Main Display using Intel 87c51 of the MCS51 family by driving a 128 X 240 pixel Graphical LCD display (in built controller HD61830 from Densitron) using assembly level language of the micro-controller.


Relevant Information

Good domain knowledge of CDMA and USB architectures.


Presented technical Papers on Wireless Application Protocol (W@P) and Global Positioning System (GPS) at national level inter college technical symposiums and have received appreciation.


Won many awards and appreciation for electronics circuit hobby project exhibitions.


Attended a weeklong course on Digital Signal Processor ADSP 2181.


Personal Profile

Date of Birth : March 24th, 1978.

Language Known : English, Hindi and Bengali.

Hobbies : Learning about recent trends in technology.

Marital Status : Unmarried.


I hereby declare that the above information is true to the best of my knowledge.


Place : Bangalore

Date : 9th June 2002


[Sayandeep Nag]


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