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Subject: Circuit Design-SRAM

Date: 04/08/02 at 8:23 PM
Posted by: V.T
E-mail: vtailor@bigfoot.com
Message Posted:

SR. CIRCUIT DESIGN ENGINEER Bay area
Experience in memory design, including ROM, single port and dual-port SRAM,
Cache and Register File area. Good knowledge of simulation tools and memory
critical path simulation methodology to characterize timing and power
specification. BSEE/MSEE

Vijay Tailor
1-888-743-4206
vtailor@bigfoot.com


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