PLL FUNCTION SPECIALIST Bay area
Develop state of the art PLLs for clock generation, clock synchronization and clock and data recovery to be ported into Barcelona Design Engine. Responsibilities include: leading a design team, managing projects and providing strong technical leadership.
MS or PhD, with at least 6 years of direct experience in PLLs design. The ideal candidate has extensive experience in the design of high performance PLLs in advanced CMOS processes, combined with a strong theoretical circuit background. The candidate should have a track record of successful design and tape out of high performance PLLs in deep sub-micron CMOS processes